Non-volatile solid state memory-based mass storage device and methods thereof
View Patent ↗Non-volatile solid state mass storage device and methods for improving write performance thereof. The storage device includes a NAND flash controller, an array of NAND flash memory integrated circuits, and means for determining a lowest unused page number of each write target block in a group of the NAND flash memory integrated circuits that are simultaneously accessible at any given time by a write command. The storage device has further means for programming a dummy write to at least a first write target block in a first NAND flash memory integrated circuit within the group of NAND flash memory integrated circuits if the lowest unused page number within the first write target block is lower than the lowest unused page number of a second write target block in a second NAND flash memory integrated circuit in the group of NAND flash memory integrated circuits.
1. A non-volatile solid state mass storage device comprising:
a substrate;
an array of NAND flash memory integrated circuits mounted on the substrate, wherein the NAND flash memory integrated circuits are organized into blocks comprising pages that contain cells and are adapted for storing more than one bit per cell including at least a first bit logically assigned to a first page and at least a second bit logically assigned to a second page, the second page being characterized by slower write times that the first page, wherein each of the NAND flash memory integrated circuits has at any given time a block that is a write target block wherein the write target blocks of the NAND flash memory integrated circuits are simultaneously accessible by a write command;
a NAND flash controller adapted to have several I/O channels each functionally coupled to at least one of the NAND flash memory integrated circuits for parallel and simultaneous access of a group of the NAND flash memory integrated circuits in a single write cycle;
means for determining a lowest unused page number for each of the write target blocks in the group of NAND flash memory integrated circuits;
means for programming a dummy write to at least a first of the write target blocks in a first of the NAND flash memory integrated circuits within the group of NAND flash memory integrated circuits if the lowest unused page number within the first write target block is lower than the lowest unused page number of a second of the write target blocks in a second of the NAND flash memory integrated circuits in the group of NAND flash memory integrated circuits.
2. The non-volatile solid state mass storage device according to claim 1 , wherein the non-volatile solid state mass storage device is adapted to perform the determining of the lowest unused page numbers and programming of dummy writes during or immediately after initialization of the non-volatile solid state mass storage device.
3. The non-volatile solid state mass storage device according to claim 1 , wherein the non-volatile solid state mass storage device is adapted to perform the determining of the lowest unused page numbers and programming of dummy writes during or immediately after power-up of the non-volatile solid state mass storage device.
4. The non-volatile solid state mass storage device according to claim 1 , wherein the non-volatile solid state mass storage device is adapted to perform the determining of the lowest unused page numbers and programming of dummy writes immediately after waking up from sleep mode.
5. The non-volatile solid state mass storage device according to claim 1 , wherein the non-volatile solid state mass storage device is adapted to perform the determining of the lowest unused page numbers and programming of dummy writes during idle periods of the non-volatile solid state mass storage device.
6. A method of improving write performance of a non-volatile solid state mass storage device comprising an array of NAND flash memory integrated circuits, wherein the NAND flash memory integrated circuits are organized into blocks comprising pages that contain cells and are adapted for storing more than one bit per cell including at least a first bit logically assigned to a first page and at least a second bit logically assigned to a second page, the second page being characterized by slower write times that the first page, wherein each of the NAND flash memory integrated circuits has at any given time a block that is a write target block wherein the write target blocks of the NAND flash memory integrated circuits are simultaneously accessible by a write command, wherein non-volatile solid state mass storage device is adapted to have several I/O channels each functionally coupled to at least one of the NAND flash memory integrated circuits for parallel and simultaneous access of a group of the NAND flash memory integrated circuits in a single write cycle, the method comprising:
determining a lowest unused page number for each of the write target blocks in the group of NAND flash memory integrated circuits;
programming a dummy write to at least a first of the write target blocks in a first of the NAND flash memory integrated circuits within the group of NAND flash memory integrated circuits if the lowest unused page number within the first write target block is lower than the lowest unused page number of a second of the write target blocks in a second of the NAND flash memory integrated circuits in the group of NAND flash memory integrated circuits.
7. The method according to claim 6 , wherein determining of the lowest unused page numbers and programming of dummy writes is performed during or immediately after initialization of the non-volatile solid state mass storage device.
8. The method according to claim 6 , wherein determining of the lowest unused page numbers and programming of dummy writes is performed during or immediately after power-up of the non-volatile solid state mass storage device.
9. The method according to claim 6 , wherein determining of the lowest unused page numbers and programming of dummy writes is performed immediately after waking up from sleep mode.
10. The method according to claim 6 , wherein determining of the lowest unused page numbers and programming of dummy writes is performed during idle periods of the non-volatile solid state mass storage device.
11. A method of improving write performance of a non-volatile solid state mass storage device comprising an array of NAND flash memory integrated circuits, wherein the NAND flash memory integrated circuits are organized into blocks comprising at least two types of pages that contain cells and are adapted for storing more than one bit per cell, including at least a first bit logically assigned to a first type of page and at least a second bit logically assigned to a second type of page, the second type of page being characterized by slower write times that the first type of page, wherein each of the NAND flash memory integrated circuits has at any given time a block that is a write target block wherein the write target blocks of the NAND flash memory integrated circuits are simultaneously accessible by a write command, wherein the non-volatile solid state mass storage device is adapted to distinguish between the at least two types of pages and to have several I/O channels each functionally coupled to at least one of the NAND flash memory integrated circuits for parallel and simultaneous access of a group of the NAND flash memory integrated circuits in a single write cycle, the method comprising:
determining a lowest unused page number for each of the write target blocks in the group of NAND flash memory integrated circuits;
associating the page with the lowest unused page number of each of the write target blocks in the group of NAND flash memory integrated circuits with a type of page; and then,
programming a dummy write to at least a first of the write target blocks in a first of the NAND flash memory integrated circuits if the page with the lowest unused page number of the first write target block belongs to a different type of page than the lowest unused page in a second of the write target blocks in a second of the NAND flash memory integrated circuits within the group of NAND flash memory integrated circuits.
12. The method according to claim 11 , wherein the page the lowest unused number is associated with a page type by comparing the lowest unused page number of each of the write target blocks against a page pairing reference for the NAND flash memory integrated circuits.
13. The method according to claim 11 , wherein determining the lowest unused page number, associating the page with a type of page, and programming of dummy writes is performed during or immediately after initialization of the non-volatile solid state mass storage device.
14. The method according to claim 11 , wherein determining the lowest unused page number, associating the page with a type of page, and programming of dummy writes is performed during or immediately after power-up of the non-volatile solid state mass storage device.
15. The method according to claim 11 , wherein determining the lowest unused page number, associating the page with a type of page, and programming of dummy writes is performed immediately after waking up from sleep mode.
16. The method according to claim 11 , wherein determining the lowest unused page number, associating the page with a type of page, and programming of dummy writes is performed during idle periods of the non-volatile solid state mass storage device.
17. A method of improving write performance of a non-volatile solid state mass storage device comprising an array of NAND flash memory integrated circuits, wherein the NAND flash memory integrated circuits are organized into blocks comprising pages that contain cells and are adapted for storing more than one bit per cell including at least a first bit logically assigned to a first page and at least a second bit logically assigned to a second page, the second page being characterized by slower write times that the first page, wherein each of the NAND flash memory integrated circuits has at any given time a block that is a write target block wherein the write target blocks of the NAND flash memory integrated circuits are simultaneously accessible by a write command, wherein the non-volatile solid state mass storage device is adapted to have several I/O channels each functionally coupled to at least one of the NAND flash memory integrated circuits for parallel and simultaneous access of a group of the NAND flash memory integrated circuits in a single write cycle, the method comprising:
determining a lowest unused page number for each of the write target blocks in the group of NAND flash memory integrated circuits;
during a first write cycle, writing to at least a first of the write target blocks in a first of the NAND flash memory integrated circuits within the group of NAND flash memory integrated circuits if the lowest unused page number within the first write target block is lower than the lowest unused page number of a second of the write target blocks in a second of the NAND flash memory integrated circuits in the group of NAND flash memory integrated circuits and not writing to the second write target block.
18. The method according to claim 17 , wherein all write target blocks have the same lowest unused page number after the first write cycle.
19. The method according to claim 17 , wherein all subsequent write cycles can use all I/O channels simultaneously after the first write cycle.