Information processing system including semiconductor device having self-refresh mode
View Patent ↗Disclosed herein is a semiconductor device having first and second operation modes. In the first operation mode, the semiconductor device deactivates a DLL circuit during a self-refresh mode. In the second operation mode, the semiconductor device intermittently activates the DLL circuit to generate an internal clock signal.
1. An information processing system comprising:
a first device including a memory cell array that holds storage data, an input buffer circuit to which an external clock signal having a predetermined frequency is supplied, and a DLL circuit that generates an internal clock signal that is phase-controlled based on the external clock signal, the first device having a self-refresh mode in which a refresh operation of the storage data is periodically performed asynchronously with the external clock signal; and
a second device issuing the external clock signal, a self-refresh command that causes the first device to enter the self-refresh mode, and a self-refresh exit command that causes the first device to exit the self-refresh mode, wherein
the second device continuously issues the external clock signal to the first device while the first device is in the self-refresh mode, and
the first device intermittently activates the input buffer circuit and the DLL circuit in conjunction with each other while the first device is in the self-refresh mode.
2. The information processing system as claimed in claim 1 , wherein
each of the first and second devices has first and second operation modes,
the second device, in the first operation mode, stops issuing the external clock signal or changes the frequency thereof while the first device is in the self-refresh mode, and
the second device, in the second operation mode, continuously issues the external clock signal having the predetermined frequency without stopping the external clock signal while the first device is in the self-refresh mode.
3. The information processing system as claimed in claim 2 , wherein the first device activates the DLL circuit when the self-refresh exit command is issued in the first operation mode.
4. The information processing system as claimed in claim 3 , wherein
the first device further includes a data terminal through which the storage data is output to the second device,
the second device further issues a first command that causes the first device to perform an access operation to the memory cell array and a second command that causes the first device to output the storage data through the data terminal in synchronism with the internal clock signal or to control an impedance of the data terminal in synchronism with the internal clock signal,
the second device, in the first operation mode, issues the second command after elapse of a first period at earliest from issuing the self-refresh exit command, and
the second device, in the second operation mode, issues the second command after elapse of a second period that is shorter than the first period at earliest from issuing the self-refresh exit command.
5. The information processing system as claimed in claim 2 , wherein
the second device further issues a mode-register set command, and
the first device is set to the first or second operation mode according to the mode-register set command.
6. The information processing system as claimed in claim 2 , wherein
the second device further issues an additional signal that specifies the first or second operation mode along with the self-refresh command, and
the first device is set to the first or second operation mode according to the additional signal.
7. The information processing system as claimed in claim 2 , wherein
the first device further includes a data terminal through which the storage data is output to the second device,
the first device, in the first operation mode, periodically performs the refresh operation on n memory cells included in the memory cell array while the first device is in the self-refresh mode, and
the first device, in the second operation mode, periodically performs the refresh operation on m memory cells included in the memory cell array asynchronous with the external clock signal while the first device is in the self-refresh mode, where m is smaller than n.
8. The information processing system as claimed in claim 7 , wherein
the second device further issues a first command that causes the first device to perform an access operation to the memory cell array and a second command that causes the first device to output the storage data through the data terminal in synchronism with the internal clock signal or to control an impedance of the data terminal in synchronism with the internal clock signal,
the second device, in the first operation mode, issues the first command after elapse of a third period at earliest from issuing the self-refresh exit command, and
the second device, in the second operation mode, issues the first command after elapse of a fourth period that is shorter than the third period at earliest from issuing the self-refresh exit command.
9. The information processing system as claimed in claim 8 , wherein
the second device further issues an auto-refresh command, and
the first device, in either the first or second operation modes, performs the refresh operation on the n memory cells included in the memory cell array when the auto-refresh command is issued.
10. The information processing system as claimed in claim 1 , wherein
the first device further includes a data terminal through which the storage data is output to the second device , and
the second device further issues an impedance control signal that controls an impedance of the data terminal while the first device is in the self-refresh mode.
11. The information processing system as claimed in claim 10 , wherein
the second device issues the impedance control signal asynchronously with the external clock signal while the first device is in the self-refresh mode, and
the first device controls an impedance of the data terminal asynchronously with the external clock signal or the internal clock signal when the impedance control signal is issued while the first device is in the self-refresh mode.
12. The information processing system as claimed in claim 10 , wherein
the second device issues the impedance control signal synchronously with the external clock signal while the first device is in other than the self-refresh mode, and
the first device controls an impedance of the data terminal synchronously with the external clock signal while the first device is in other than the self-refresh mode.
13. The information processing system as claimed in claim 10 , wherein
each of the first and second devices has first and second operation modes, and
the second device, in the second operation mode, issues the impedance control signal while the first device is in the self-refresh mode.
14. The information processing system as claimed in claim 13 , wherein the second device, in the first operation mode, does not issue the impedance control signal while the first device is in the self-refresh mode.
15. The information processing system as claimed in claim 1 , further comprising a third device having substantially the same configuration as the first device, wherein
each of the first and third devices includes a clock terminal to which the external clock signal is supplied,
the clock terminals included in the first and third devices are commonly connected with each other, and
the second device supplies the external clock signal commonly to the first and third devices.
16. The information processing system as claimed in claim 1 , further comprising a third device having substantially the same configuration as the first device, wherein
each of the first and third devices includes:
a clock terminal to which the external clock signal is supplied;
a clock enable terminal to which a clock enable signal indicating whether the external clock signal is valid is supplied;
a data terminal through which the storage data is output;
an ODT terminal to which an impedance control signal that controls an impedance of the data terminal is supplied; and
a chip select terminal to which a chip select signal that selects an associated one of the first and third devices is supplied,
the clock terminals included in the first and third devices are commonly connected with each other,
the data terminals included in the first and third devices are commonly connected with each other,
the clock enable terminals included in the first and third devices are electrically independent of each other,
the ODT terminals included in the first and third devices are electrically independent of each other,
the chip select terminals included in the first and third devices are electrically independent of each other,
the second device supplies the external clock signal commonly to the first and third devices, and
the second device supplies different one of the clock enable signals, different one of the impedance control signals, different one of the chip select signals to the first and third devices, respectively.
17. The information processing system as claimed in claim 1 , further comprising a third device having substantially the same configuration as the first device, wherein
each of the first and third devices includes:
a clock terminal to which the external clock signal is supplied;
a clock enable terminal to which a clock enable signal indicating whether the external clock signal is valid is supplied;
a data terminal through which the storage data is output;
an ODT terminal to which an impedance control signal that controls an impedance of the data terminal is supplied; and
a chip select terminal to which a chip select signal that selects an associated one of the first and third devices is supplied,
the data terminals included in the first and third devices are commonly connected with each other,
the clock terminals included in the first and third devices are electrically independent of each other
the clock enable terminals included in the first and third devices are electrically independent of each other,
the ODT terminals included in the first and third devices are electrically independent of each other,
the chip select terminals included in the first and third devices are electrically independent of each other, and
the second device supplies different one of the external clock signals, different one of the clock enable signals, different one of the impedance control signals, and different one of the chip select signals to the first and third devices, respectively.
18. The information processing system as claimed in claim 16 , wherein the self-refresh exit command is expressed by using the clock enable signal.
19. The information processing system as claimed in claim 16 , wherein the first and third devices are mounted on different module substrates.
20. The information processing system as claimed in claim 1 , wherein the first device further includes a data terminal through which the storage data is output to the second device.