System and method for decreasing signal integrity noise by using varying drive strengths based on likelihood of signals becoming victims
View Patent ↗A method of designing an integrated circuit, integrated circuits using different drive strengths and a signal integrity monitor are provide herein. In one embodiment, the signal integrity monitor includes: (1) a signal interface configured to receive a signal from a parallel data bus for transmission over a plurality of signal paths and (2) a victim signal identifier configured to dynamically determine a potential victim signal path of the plurality of signal paths.
1. A method of designing an integrated circuit, comprising:
identifying a signal path that is a potential victim signal path, wherein said signal path is positioned between a bus driver of a first component of said integrated circuit to an interface terminal of a second component of said integrated circuit; and
increasing via a processor an effective drive strength of an interface driver of said potential victim signal path, wherein said increasing includes changing a drive strength of an interface driver of at least one signal path adjacent to said potential victim signal path.
2. The method as recited in claim 1 wherein said increasing includes reducing a drive impedance of said interface driver of said potential victim signal path.
3. The method as recited in claim 1 wherein said increasing includes increasing a drive impedance of said interface driver of said at least one signal path adjacent to said potential victim signal path.
4. The method as recited in claim 1 wherein said signal path is one of a plurality of signal paths coupled to interface terminals of said first component.
5. The method as recited in claim 4 wherein said method further includes analyzing a layout of said integrated circuit and spatial relationships of said layout between said plurality of signal paths, said first component and said second component.
6. The method as recited in claim 4 wherein said identifying includes analyzing signals for transmission on said plurality of signal paths.
7. The method as recited in claim 1 further comprising simulating said integrated circuit after increasing said effective drive strength and implementing said effective drive strength based on said simulating.
8. A signal integrity monitor, comprising:
a signal interface configured to receive a signal from a parallel data bus for transmission over a plurality of signal paths;
a victim signal identifier configured to dynamically determine a potential victim signal path of said plurality of signal paths; and
a drive strength controller configured to generate a drive control to adjust an effective drive strength of at least one interface driver corresponding to at least one of said plurality of signal paths and associated with said potential victim signal path.
9. The signal integrity monitor as recited in claim 8 wherein said victim signal identifier is configured to dynamically determine said potential victim signal path based on an order of external interface terminals uniquely associated with said plurality of signal paths.
10. The signal integrity monitor as recited in claim 8 wherein said victim signal identifier is configured to dynamically determine said potential victim signal path based on a pattern of said signal.
11. The signal integrity monitor as recited in claim 8 wherein said victim signal identifier is further configured to dynamically determine said potential victim signal path based on relative transitions of bits, relative to one another, of said plurality of signal paths for each operating.
12. The signal integrity monitor as recited in claim 8 wherein said victim signal identifier is configured to dynamically determine potential victim signal paths associated with each bit of said signal for each operating cycle associated with said signal.
13. The signal integrity monitor as recited in claim 12 wherein said victim signal identifier is configured to dynamically determine said potential victim signal path based on a transition pattern of said signal at each said cycle.
14. The signal integrity monitor as recited in claim 8 wherein said drive strength controller is configured to adjust said effective drive strength before said signal is delivered to said plurality of signal paths.
15. An integrated circuit, comprising:
a parallel bus configured to transmit a signal;
a plurality of signal paths coupled to said parallel bus;
a plurality of interface drivers uniquely coupled to said parallel bus and said plurality of signal paths, wherein said plurality of interface drivers are configured to drive said signal along said plurality of signal paths; and
a signal integrity monitor coupled to said parallel bus and said plurality of interface drivers, said signal integrity monitor including:
a signal interface configured to receive said signal from said parallel bus; and
a victim signal identifier configured to dynamically determine a potential victim signal path of said plurality of signal paths based on said signal.
16. The integrated circuit as recited in claim 15 further comprising a drive strength controller configured to generate a drive control to adjust an effective drive strength of at least one interface driver corresponding to one of said plurality of signal paths and associated with said potential victim signal path before said signal is delivered to said plurality of signal paths.
17. The integrated circuit as recited in claim 15 wherein said victim signal identifier is configured to dynamically determine said potential victim signal path based on a pattern of said signal.
18. The integrated circuit as recited in claim 15 wherein said victim signal identifier is further configured to dynamically determine said potential victim signal path based on an order of external interface terminals uniquely associated with said plurality of signal paths.
19. The integrated circuit as recited in claim 15 wherein said victim signal identifier is configured to dynamically determine potential victim signal paths associated with each bit of said signal for each operating cycle associated with said signal.
20. The integrated circuit as recited in claim 19 wherein said victim signal identifier is configured to dynamically determine said potential victim signal path based on a transition pattern of said signal at each said cycle.
21. An integrated circuit, comprising:
a parallel interface;
a plurality of interface drivers configured to drive a signal along a plurality of signal path associated with said parallel interface;
a victim signal identifier configured to dynamically determine a potential victim signal path of said plurality of signal paths; and
a drive strength controller configured to generate a drive control to adjust an effective drive strength of at least one of said plurality of interface drivers corres ponding to at least one of said plurality of signal paths and associated with said potential victim signal path.
22. The integrated circuit as recited in claim 21 wherein said integrated circuit is a chip of a package on a printed circuit board.