Suppressing intra-cell interference

1. A system having a feedback loop, the feedback loop comprising:

an interference suppression module comprising an inter-cell interference suppression module to suppress inter-cell interference, the interference suppression module further comprising an intra-cell interference suppression module to suppress intra-cell interference;

a pre-equalization (pre-EQ) module coupled to an output of the interference suppression module;

a chip equalization (chip-EQ) weight calculation module coupled to an output of the pre-EQ module;

a delay match module coupled to the output of the pre-EQ module;

a chip-level equalization (chip-EQ) module coupled to an output of the chip-EQ weight calculation module, the chip-EQ module further being coupled to an output of the delay match module;

a downlink shared channel (DSCH) despreader coupled to an output of the chip-EQ module;

a shared control channel (SCCH) despreader coupled to an output of the chip-EQ weight calculation module; and

a high-speed (HS) shared control channel (SCCH) decoding module coupled to an output of the SCCH module, wherein an output of the HS-SCCH decoding module is coupled to the DSCH module, wherein the output of the HS-SCCH is further coupled to the interference suppression module.

2. The system of claim 1 , wherein the intra-cell interference suppression module comprises:

a code gate configured to gate out channel information for a specified rake finger and pass through remaining information unrelated to the specified rake finger; and

a residual channel signal reconstruction circuit configured to produce a reconstructed residual channel signal from the remaining information, wherein the residual channel signal is uncorrelated to the channel information for the specified rake finger.

3. The system of claim 2 , wherein the intra-cell interference suppression module further comprises:

a rake finger signal reconstruction circuit configured to produce a reconstructed rake finger channel signal from the channel information; and

a subtractor configured to subtract the residual channel signal from the rake finger channel signal to produce an intra-cell interference-suppressed signal.

4. The system of claim 3 , wherein the intra-cell interference suppression module further comprises:

a rake finger Inverse Fast Hadamard Transform (IFHT) module configured to produce rake finger IFHT information by performing an IFHT on the channel information;

a rake finger scrambler configured to produce rake finger scrambled information by scrambling the rake finger IFHT information; and

a rake finger channel rotation module configured to produce the reconstructed rake finger channel signal from the scrambled information.

5. A method for suppressing interference, comprising:

receiving intra-cell interference signals for a specified rake finger;

receiving inter-cell interference signals;

receiving feedback from a decoding module;

suppressing the intra-cell interference signals upstream of a chip-level equalizer using the feedback from the decoding module; and

suppressing the inter-cell interference signals upstream of the chip-level equalizer.

6. The method of claim 5 , wherein suppressing the intra-cell interference signals comprises:

gating out rake finger information for the specified rake finger, wherein the rake finger information comprises rake finger control information, wherein the rake finger information further comprises rake finger channel data; and

passing through remaining information, wherein the remaining information is substantially uncorrelated to the specified rake finger.

7. The method of claim 6 , wherein suppressing the intra-cell interference signals further comprises:

reconstructing a residual signal from the remaining information, wherein the residual signal is substantially uncorrelated to the rake finger information;

reconstructing an estimated rake finger channel signal from the rake finger information; and

subtracting the residual signal from the estimated rake finger channel signal to produce an intra-cell interference-suppressed signal.

8. The method of claim 7 , wherein reconstructing the residual signal comprises:

inverse fast Hadamard transforming (IFHT) the remaining information to produce residual IFHT information;

scrambling the residual IFHT information to produce residual scrambled information; and

estimating the residual signal from the residual scrambled information.

9. The method of claim 7 , wherein reconstructing the estimated rake finger signal comprises:

inverse fast Hadamard transforming (IFHT) the rake finger information to produce rake finger IFHT information;

scrambling the rake finger IFHT information to produce rake finger scrambled information; and

estimating the rake finger channel signal from the rake finger scrambled information.

10. A system for suppressing interference, comprising:

a chip-level equalizer;

a decoding module located upstream of the chip-level equalizer; and

an interference suppression module located upstream of the chip-level equalizer, wherein the interference suppression module is configured to receive inter-cell interference signals, wherein the interference suppression module is further configured to receive intra-cell interference signals, wherein the interference suppression module comprises:

an inter-cell interference suppression module configured to suppress the inter-cell interference signals; and

an intra-cell interference suppression module configured to suppress the intra-cell interference signals using a feedback from the decoding module.

11. The system of claim 10 , wherein the intra-cell interference suppression module comprises:

a code gate configured to gate out channel information for a specified rake finger and pass through remaining information unrelated to the specified rake finger; and

a residual channel signal reconstruction circuit configured to produce a reconstructed residual channel signal from the remaining information, wherein the residual channel signal is substantially uncorrelated to the channel information for the specified rake finger.

12. The system of claim 11 , wherein the residual channel signal reconstruction circuit comprises:

a residual channel signal Inverse Fast Hadamard Transform (IFHT) module configured to produce residual IFHT information by performing an IFHT on the remaining information;

a residual channel signal scrambler configured to produce residual scrambled information by scrambling the residual IFHT information; and

a residual channel rotation module configured to produce the reconstructed residual channel signal from the scrambled information.

13. The system of claim 11 , wherein the intra-cell interference suppression module further comprises a rake finger signal reconstruction circuit configured to produce a reconstructed rake finger channel signal from the channel information.

14. The system of claim 13 , wherein the intra-cell interference suppression module further comprises:

a rake finger Inverse Fast Hadamard Transform (IFHT) module configured to produce rake finger IFHT information by performing an IFHT on the channel information;

a rake finger scrambler configured to produce rake finger scrambled information by scrambling the rake finger IFHT information; and

a rake finger channel rotation module configured to produce the reconstructed rake finger channel signal from the scrambled information.

15. The system of claim 13 , wherein the intra-cell interference suppression module further comprises a subtractor configured to subtract the residual channel signal from the rake finger channel signal to produce an intra-cell interference-suppressed signal.

16. The system of claim 10 , further comprising:

a pre-equalization (pre-EQ) module comprising a pre-EQ input and a pre-EQ output, wherein the pre-EQ input is coupled to an output of the interference suppression module;

a chip equalization (chip-EQ) weight calculation module comprising a chip-EQ weight calculation input and a chip-EQ weight calculation output, wherein the chip-EQ weight calculation input is coupled to the pre-EQ output;

a delay match module comprising a delay match module input and a delay match module output, wherein the delay match module input is coupled to the pre-EQ output; and

a chip-level equalization (chip-EQ) module comprising a chip-EQ input and a chip-EQ output, wherein the chip-EQ input is coupled to the chip-EQ weight calculation output, wherein the chip-EQ input is further coupled to the delay match module output.

17. The system of claim 16 , further comprising a downlink shared channel (DSCH) despreader comprising a DSCH input and a DSCH output, wherein the DSCH input is coupled to the chip-EQ output.

18. The system of claim 17 , further comprising a shared control channel (SCCH) despreader comprising a SCCH input and a SCCH output, wherein the SCCH input is coupled to the chip-EQ weight calculation output.

19. The system of claim 18 , further comprising a high-speed (HS) shared control channel (SCCH) decoding module comprising a HS-SCCH input and a HS-SCCH output, wherein the HS-SCCH input is coupled to the SCCH output, wherein the HS-SCCH output is coupled to the DSCH input, wherein the HS-SCCH output is further coupled to an input of the interference suppression module.

20. The system of claim 19 , wherein the HS-SCCH output is further coupled to an input of the intra-cell interference suppression module.