IP Library Granted Patent US 8,526,487
Granted Patent B1
US 8,526,487 · App. 13/560,141 · Granted Sep 3, 2013

Differential energy difference integrator

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Quick Facts
Patent No.
US 8,526,487
App. No.
13/560,141
Granted
Sep 3, 2013
Kind
B1
Abstract

Embodiments of the invention are generally directed to a high-speed differential energy difference integrator (EDI) for adaptive equalizers. In an embodiment, the EDI includes two differential full-wave rectifiers providing differential outputs that are cross-coupled to the inputs of an integration capacitor. In one embodiment, the active areas of the transistors of the differential full-wave rectifiers are substantially the same.

Claims (55)

1. An equalizer circuit comprising:

an inverse cable filter to receive a signal from a transmission line;

a slicer coupled with the inverse cable filter to receive an output from the inverse cable filter; and

an energy difference integrator coupled to receive as a first input the output from the inverse cable filter and coupled to receive as a second input an output from the slicer, wherein the energy difference integrator is configured to perform an integration of differential signals and to provide a fully differential feedback control signal to the inverse cable filter, and wherein the energy difference integrator comprises a first full-wave rectifier, wherein the first full-wave rectifier comprises a plurality of transistors each having an active area that is substantially the same.

2. The circuit of claim 1 , wherein

the first full-wave rectifier is coupled to receive the output from the inverse cable filter, the first full-wave rectifier having a first differential current output including a first current output and a second current output, and wherein the energy difference integrator comprises:

a second full-wave rectifier coupled to receive the output from the slicer, the second full-wave rectifier having a first differential current output including a first current output and second current output; and

an integrator having a first terminal and a second terminal, wherein the first current output of the first full-wave rectifier and the second current output of the second full-wave rectifier are coupled with the first terminal and the second current output of the first full-wave rectifier and the first current output of the second full-wave rectifier are coupled with the second terminal.

3. The circuit of claim 2 , wherein the energy difference integrator further comprises:

a common-mode feedback circuit coupled with the first terminal and the second terminal of the integrator to provide the fully differential feedback control signal to the inverse cable filter.

4. The circuit of claim 2 , wherein at least one of the first and second full-wave rectifiers comprises:

a first differential pair of transistors each transistor of the first differential pair having an active area A; and

a second differential pair of transistors each transistor of the second differential pair having an active area A, wherein the active area A of all four transistors is substantially the same.

5. The circuit of claim 4 , wherein:

the first differential pair of transistors is a first metal-oxide semiconductor field-effect transistor (MOSFET) differential pair of transistors; and

the second differential pair of transistors is a second MOSFET differential pair of transistor.

6. The circuit of claim 4 , wherein:

the first differential pair of transistors is a first bipolar junction transistor (BJT) differential pair of transistors; and

the second differential pair of transistors is a second BJT differential pair of transistors.

7. The circuit of claim 6 , wherein:

the first BJT differential pair of transistors is a first emitter-coupled differential pair of transistors; and

the second BJT differential pair of transistors is a second emitter-coupled differential pair of transistors.

8. A method comprising:

receiving an output of inverse cable filter;

receiving an output of a slicer;

integrating, by an energy difference integrator, the output of the inverse cable filter and the output of the slice as differential signals;

wherein the energy difference integrator comprises a first full-wave rectifier, wherein the first full-wave rectifier comprises a plurality of transistors each having an active area that is substantially the same; and

generating, by the energy difference integrator, a fully differential feedback control signal, based on the integrated outputs of the inverse cable filter and the slicer.

9. The method of claim 8 , further comprising:

providing the fully differential feedback control signal to the inverse cable filter.

10. The method of claim 8 , wherein the inverse cable filter receives a signal from a transmission line.

11. The method of claim 8 , wherein the slicer receives the output of the inverse cable filter.

12. The method of claim 8 , wherein

the first full-wave rectifier is coupled to receive the output from the inverse cable filter, the first full-wave rectifier having a first differential current output including a first current output and a second current output, and wherein the energy difference integrator comprises:

a second full-wave rectifier coupled to receive the output from the slicer, the second full-wave rectifier having a first differential current output including a first current output and second current output; and

an integrator having a first terminal and a second terminal, wherein the first current output of the first full-wave rectifier and the second current output of the second full-wave rectifier are coupled with the first terminal and the second current output of the first full-wave rectifier and the first current output of the second full-wave rectifier are coupled with the second terminal.

13. The method of claim 12 , wherein the energy difference integrator further comprises:

a common-mode feedback circuit coupled with the first terminal and the second terminal of the integrator to provide the fully differential feedback control signal to the inverse cable filter.

14. The method of claim 12 , wherein at least one of the first and second full-wave rectifiers comprises:

a first differential pair of transistors each transistor of the first differential pair having an active area A; and

a second differential pair of transistors each transistor of the second differential pair having an active area A, wherein the active area A of all four transistors is substantially the same.

15. The method of claim 14 , wherein:

the first differential pair of transistors is a first metal-oxide semiconductor field-effect transistor (MOSFET) differential pair of transistors; and

the second differential pair of transistors is a second MOSFET differential pair of transistor.

16. The method of claim 14 , wherein:

the first differential pair of transistors is a first bipolar junction transistor (BJT) differential pair of transistors; and

the second differential pair of transistors is a second BJT differential pair of transistors.

17. The method of claim 16 , wherein:

the first BJT differential pair of transistors is a first emitter-coupled differential pair of transistors; and

the second BJT differential pair of transistors is a second emitter-coupled differential pair of transistors.

18. An apparatus comprising:

an inverse cable filter;

a slicer coupled to the inverse cable filter;

an output driver coupled to the slicer; and

an energy difference integrator coupled to the cable filter and the slicer, the energy difference integrator comprising a first full-wave rectifier, a second full-wave rectifier, and an integration capacitor, the first and second full-wave rectifiers having current outputs that are cross-coupled to perform an integration of differential signals and to provide a differential current to drive the integration capacitor, wherein at least one of the first and second full-wave rectifier comprises a plurality of transistors each having an active area that is substantially the same.

Assignments (5)
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2016
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MONTEREY RESEARCH, LLC
Reel/Frame 040911/0238 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS Recorded Aug 11, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 039708/0001 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2014
From: VECERA, DUSAN
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 034546/0412 →