IP Library Patent Application 13560519
Patent Application
App. No. 13/560,519

ADAPTIVE FREQUENCY COMPENSATION FOR PFC POWER CONVERTER OPERATING IN CCM AND DCM

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Quick Facts
Patent No.
US None
App. No.
13/560,519
Abstract

A control circuit of a power factor correction (PFC) converter is provided. The control circuit includes a pulse width modulation (PWM) circuit, an amplifier, a detection circuit., and a capacitor. The PWM circuit generates a switching signal in response to a loop signal. The amplifier is coupled to generate the loop signal in response to a switching current. The detection circuit generates a mode signal coupled to change output impedance of the amplifier. The capacitor is coupled to the amplifier for loop frequency compensation. The switching signal is coupled to switch an inductor of the PFC power converter and generate the switching current.

Claims (25)

1 . A control circuit of a power factor correction (PFC) converter comprising:

a pulse width modulation (PWM) circuit generating a switching signal in response to a loop signal;

an amplifier coupled to receive a switching current for generating the loop signal;

a detection circuit generating a mode signal coupled to change output impedance of the amplifier; and

a capacitor coupled to the amplifier for loop frequency compensation;

wherein the switching signal is coupled to switch an inductor of the PFC power converter and generate the switching current.

2 . The circuit as claimed in claim 1 , wherein the mode signal indicates a CCM (continuous current mode) or DCM (discontinuous current mode) operation.

3 . The circuit as claimed in claim 1 , wherein the mode signal is generated in response to an input voltage of the PFC power converter, an output voltage of the PFC power converter, and the switching signal.

4 . The circuit as claimed in claim 1 , wherein the amplifier is a transconductance amplifier.

5 . The circuit as claimed in claim 1 , wherein the mode signal is coupled to change a bias current of the amplifier.

6 . The circuit as claimed in claim 1 , wherein the loop signal is a current loop signal generated by comparing the switching current with a command signal.

7 . The circuit as claimed in claim 6 , wherein the command signal is generated

8 . A method for controlling a power factor correction (PFC) converter comprising:

generating a switching signal in response to a loop signal;

generating the loop signal in accordance with a switching current;

generating a mode signal coupled to change the impedance of the loop signal;

compensating the loop signal with a capacitor;

wherein the switching signal is coupled to switch an inductor of the PFC power converter and generate the switching current.

9 . The method as claimed in claim 8 , wherein the mode signal indicates a CCM (continuous current mode) or DCM (discontinuous current mode) operation.

10 . The method as claimed in claim 8 , wherein the mode signal is generated in response to an input voltage of the PFC power converter, an output voltage of the PFC power converter, and the switching signal.

11 . The method as claimed in claim 8 , wherein the loop signal is generated by a transconductance amplifier.

12 . The method as claimed in claim 8 , wherein the mode signal is coupled to change a bias current of the transconductance amplifier.

13 . The method as claimed in claim 8 , wherein the loop signal is a current loop signal generated by comparing the switching current with a command signal.

14 . The method as claimed in claim 13 , wherein the command signal is generated in response to an input voltage of the PFC power converter.

15 . The method as claimed in claim 8 , wherein the impedance associated with the loop signal and capacitance of the capacitor develop a low-pass filter for the loop signal.

Assignments (5)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT RECORDED AT REEL 046410, FRAME 0933 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064072/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 22, 2018
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 046410/0933 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 25, 2017
From: FAIRCHILD (TAIWAN) CORPORATION (FORMERLY SYSTEM GENERAL CORPORATION)
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 042328/0318 →
CHANGE OF NAME Recorded May 3, 2016
From: SYSTEM GENERAL CORPORATION
To: FAIRCHILD (TAIWAN) CORPORATION
Reel/Frame 038599/0078 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 27, 2012
From: YANG, TA-YUNG; CHEN, YING-CHI; HSU, CHIEN-TSUN; CHEN, CHENG-SUNG
To: SYSTEM GENERAL CORPORATION
Reel/Frame 028660/0269 →