Static RAM

1. A static random access memory (RAM) comprising:

a plurality of word lines;

a plurality of pairs of local bit lines;

a plurality of memory cells arranged in correspondence with intersections of the plurality of pairs of local bit lines and the plurality of word lines;

a plurality of capacitance shared circuits each arranged for each of the plurality of pairs of local bit lines;

a common connection line connecting the plurality of capacitance shared circuits; and

a pair of global bit lines connected to the plurality of pairs of local bit lines, wherein:

each capacitance shared circuit comprises two N-channel transistors connected between the pair of local bit lines and the common connection line corresponding to each other,

a drain of one of the two N-channel transistors is connected to one of the pair of local bit lines,

a drain of the other of the two N-channel transistors is connected to the other of the pair of local bit lines, and

sources of the two N-channel transistors are connected to the common connection line.

2. The static RAM according to claim 1 , wherein:

the plurality of memory cells are connected to a corresponding pair of local bit lines in accordance with a row selection signal to be applied to a word line of the plurality of word lines,

when the plurality of local bit lines are placed into a state based on contents stored in the memory cell of each pair of local bit lines by applying the row selection signal to the word line corresponding to a memory cell to be selected, the capacitance shared circuit corresponding to each pair of local bit lines places one of the two N-channel transistors into a conduction state in accordance with a potential of the corresponding pair of local bit lines and places the other N-channel transistor into a cut-off state,

the N channel transistor to be connected to the local bit line on a low potential side of the two N-channel transistors is placed into the conduction state, and

the local bit lines on a low potential side of the plurality of pairs of local bit lines are connected to one another via the common connection line.

3. The static RAM according to claim 2 , wherein:

application of the row selection signal is stopped in a state where the local bit lines on the low potential side of the plurality of pairs of local bit lines are connected to one another,

a state of the pair of global bit lines is changed by connecting one of the pair of global bit lines to a local bit line on the high potential side of the pair of local bit lines of a selected column and the other global bit line to a local bit line on the low potential side of the plurality of pairs of local bit lines connected via the local bit line on the low potential side of the selected column and the common connection line, and

the global sense amplifier is operated.

4. The static RAM according to claim 3 , wherein the plurality of capacitance shared circuits each include a local sense amplifier provided for each of the plurality of pairs of local bit lines and started by a common local sense amplifier start signal.

5. The static RAM according to claim 4 , wherein:

the local sense amplifier comprises the two N-channel transistors, and

when the plurality of pairs of local bit lines are placed into a state in accordance with the contents stored in the memory cell of each pair of local bit lines, each of the local sense amplifiers is started by applying the local sense amplifier start signal.