Spur reduction circuit

1. A circuit for modulating an input signal comprising;

an offset generator configured to form the input signal by adding an offset to an initial signal;

a dither signal generator configured to generate a first dither signal having a maximum amplitude;

a deamplifier configured to reduce the amplitude of said input signal so as to generate a deamplified input signal having a maximum amplitude that is comparable to the maximum amplitude of the dither signal; and

a summer configured to sum the dither signal with the deamplified input signal.

2. A circuit as claimed in claim 1 wherein the summer is configured to output a summed signal and wherein the circuit further comprises a first modulator configured to modulate the summed signal.

3. A circuit as claimed in claim 2 wherein the first modulator is configured to output a modulated signal, the modulated signal comprising a dither component, and wherein the circuit further comprises a canceller configured to at least partially cancel the dither component from the first modulated signal to form a cancelled signal.

4. A circuit as claimed in claim 3 wherein the circuit comprises an amplifier configured to amplify the cancelled signal.

5. A circuit as claimed in claim 1 , wherein the dither signal generator is further configured to generate a second dither signal, the circuit further comprising another summer configured to subtract the second dither signal from the deamplified input signal.

6. A circuit as claimed in claim 5 wherein the summer is configured to output a summed signal and wherein the circuit further comprises a first modulator configured to modulate the summed signal the first modulator is configured to output a modulated signal, the modulated signal comprising a dither component, and wherein the circuit further comprises a canceller configured to at least partially cancel the dither component from the first modulated signal to form a cancelled signal and wherein the circuit further comprises a second modulator configured to receive and modulate a summer signal output by the other summer and to output a modulated signal in dependence thereon.

7. A circuit as claimed in claim 6 wherein the canceller and the amplifier are implemented by an adder configured to add the first and second modulated signals together.

8. A circuit a claimed in claim 6 wherein the first and second modulators are digital modulators.

9. A circuit as claimed in claim 6 wherein the first and second modulators are delta-sigma modulators.

10. A circuit as claimed in claim 5 wherein the first and second dither signals are the same signal.

11. A circuit as claimed in claim 1 wherein the dither signal generator is further configured to generate a second dither signal, the circuit further comprising another summer configured to add the second dither signal to the deamplified input signal.

12. A circuit as claimed in claim 11 wherein the summer is configured to output a summed signal and wherein the circuit further comprises a first modulator configured to modulate the summed signal, the first modulator is configured to output a modulated signal, the modulated signal comprising a dither component, and wherein the circuit further comprises a canceller configured to at least partially cancel the dither component from the first modulated signal to form a cancelled signal and wherein the circuit further comprises a second modulator configured to receive and modulate a summed signal output by the other summer and to output a second modulated signal in dependence thereon.

13. A circuit as claimed in claim 1 wherein the first dither signal has the form r[n] and the second dither signal has the form −r[n].

14. A circuit as claimed in claim 1 wherein the dither signal generator comprises a pseurorandom number generator for generating the dither signals.

15. A circuit as claimed in claim 1 wherein the circuit further comprises an offset-summer configured to effectively subtract the offset from the first modulated signal.

16. A circuit as claimed in claim 1 wherein the first dither signal has an average amplitude of zero.

17. A circuit as claimed in claim 1 wherein the circuit has a maximum noise level associated therewith and the dither signal generator is configured to generate the first dither signal to have a maximum amplitude that is dependent on the maximum noise level.

18. A circuit as claimed in claim 1 wherein the maximum amplitude of the dither signal is at least 80% of the maximum amplitude of the deamplified input signal.

19. A circuit as claimed in claim 1 wherein the maximum amplitude of the dither signal is at least 90% of the maximum amplitude of the deamplified input signal.

20. A circuit as claimed in claim 1 wherein the maximum amplitude of the dither signal is the same as the maximum amplitude of the deamplified input signal.

21. An audio system comprising a circuit as claimed in claim 1 .

22. A phase locked loop comprising a circuit as claimed in claim 1 .

23. A method for modulating an input signal in a circuit configured to receive an input signal to be modulated, comprising the steps of;

forming the input signal by adding an offset to an initial signal;

generating a dither signal having a maximum amplitude;

reducing the amplitude of said input signal so as to generate a deamplified input signal having a maximum amplitude that is comparable to the maximum amplitude of the dither signal; and

summing the dither signal with the deamplified input.

24. A circuit for applying a dither signal comprising:

a first signal path comprising:

a first input configured to receive an initial signal;

an offset generator configured to form an input signal by adding an offset to the initial signal;

a first summer configured to produce a first summed signal by summing a dither signal with the input signal; and

a first modulator configured to receive and modulate the first summed signal by subtracting the dither signal from the input signal; and

a second signal path comprising:

a second input configured to produce a second summed signal by subtracting the dither signal from the input signal; and

a second modulator configured to receive and modulate the second summed signal so as to output a second modulated signal;

the circuit further comprising:

a canceller configured to sum the first and second modulated signals.