Semiconductor integrated circuit device having a plurality of standard cells for leakage current suppression
View Patent ↗A semiconductor integrated circuit device includes cells A-1, B-1, and C-1 that have the same logic. Cell B-1 has cell width W 2 larger than a cell width of cell A-1, but gate length L 1 of a MOS transistor is equal to that of cell A-1. Cell C-1 has cell width W 2 equal to a cell width of cell B-1, but has a MOS transistor having large gate length L 2 . A circuit delay of cell C-1 becomes large as compared with that of cells A-1 and B-1, but leak current becomes small. Therefore, by replacing cell A-1 adjacent to a space area with cell B-1, and by replacing cell B-1 in a path having room in timing with cell C-1, for example, leak current can be suppressed without increasing a chip area.
1. A semiconductor integrated circuit device arrayed with a plurality of standard cells, comprising:
a first standard cell which has a first cell width and in which a MOS transistor constituting a circuit has a first gate length;
a second standard cell which has the same logic as that of the first standard cell and has a second cell width larger than the first cell width, and in which a MOS transistor constituting a circuit has the first gate length; and
a third standard cell which has the same logic as that of the first and second standard cells and has the second cell width, and in which a shape of a gate of a MOS transistor constituting a circuit is different from that of the second standard cell, wherein
the third standard cell
includes at least one MOS transistor having a second gate length larger than the first gate length.
2. The semiconductor integrated circuit device according to claim 1 , wherein
the third standard cell
includes a MOS transistor having the first gate length, in addition to the MOS transistor having the second gate length.
3. The semiconductor integrated circuit device according to claim 1 , wherein
the second and third standard cells
have the same positional relationship of vias that are connected to a plurality of terminal wirings which become an input terminal and an output terminal.
4. The semiconductor integrated circuit device according to claim 1 , wherein
in the second and third standard cells,
a plurality of terminal wirings that become an input terminal and an output terminal are extended to a first direction, and a positional relationship of the plurality of terminal wirings in a second direction perpendicular to the first direction is the same.
5. The semiconductor integrated circuit device according to claim 1 , wherein
in the first and second standard cells,
at least one of an interval between adjacent gates, a gate width, a shape of a gate, a shape of a diffusion region, and a positional relationship between a gate and a contact is the same.
6. A semiconductor integrated circuit device arrayed with a plurality of standard cells, comprising:
a first standard cell which has a first cell width and in which a MOS transistor constituting a circuit has a first gate length;
a second standard cell which has the same logic as that of the first standard cell and has a second cell width larger than the first cell width, and in which a MOS transistor constituting a circuit has the first gate length; and
a third standard cell which has the same logic as that of the first and second standard cells and has the second cell width, and in which a shape of a gate of a MOS transistor constituting a circuit is different from that of the second standard cell, wherein
the third standard cell
includes two or more MOS transistors which correspond to one MOS transistor in the second standard cell, have the first gate lengths, are connected in series, and have the gates connected in common.
7. The semiconductor integrated circuit device according to claim 6 , wherein
the second and third standard cells
have the same positional relationship of vias that are connected to a plurality of terminal wirings which become an input terminal and an output terminal.
8. The semiconductor integrated circuit device according to claim 6 , wherein
in the second and third standard cells,
a plurality of terminal wirings that become an input terminal and an output terminal are extended to a first direction, and a positional relationship of the plurality of terminal wirings in a second direction perpendicular to the first direction is the same.
9. The semiconductor integrated circuit device according to claim 6 , wherein
in the first and second standard cells,
at least one of an interval between adjacent gates, a gate width, a shape of a gate, a shape of a diffusion region, and a positional relationship between a gate and a contact is the same.
10. A semiconductor integrated circuit device arrayed with a plurality of standard cells, comprising:
a first standard cell that has a first cell width and that includes a first parallel transistor group including two or more MOS transistors having first gate lengths, connected in parallel, and having gates connected in common, as MOS transistors constituting a circuit; and
a second standard cell that has the same logic as that of the first standard cell and has the first cell width, and that includes a second parallel transistor group corresponding to the first parallel transistor group, as MOS transistors constituting a circuit, wherein
the second parallel transistor group
includes two or more MOS transistors connected in parallel, and having gates connected in common, and includes at least one MOS transistor having the parallel number smaller than that of the first parallel transistor group and having a second gate length larger than the first gate length.
11. The semiconductor integrated circuit device according to claim 10 , wherein
the second parallel transistor group
includes a MOS transistor having the first gate length, in addition to the MOS transistor having the second gate length.
12. A semiconductor integrated circuit device arrayed with a plurality of standard cells, comprising:
a first standard cell that has a first cell width and that includes a first parallel transistor group including two or more MOS transistors having first gate lengths, connected in parallel, and having gates connected in common, as MOS transistors constituting a circuit; and
a second standard cell that has the same logic as that of the first standard cell and has the first cell width, and that includes a second parallel transistor group corresponding to the first parallel transistor group, as MOS transistors constituting a circuit, wherein
the second parallel transistor group
has two or more series-connected MOS transistors connected in parallel and having gates connected in common, and
has the parallel number smaller than that of the first parallel transistor group, with each MOS transistor having the first gate length.
13. The semiconductor integrated circuit device according to claim 10 , wherein
the first and second standard cells
have the same positional relationship of vias that are connected to a plurality of terminal wirings which become an input terminal and an output terminal.
14. The semiconductor integrated circuit device according to claim 10 , wherein
in the first and second standard cells,
a plurality of terminal wirings that become an input terminal and an output terminal are extended to a first direction, and a positional relationship of the plurality of terminal wirings in a second direction perpendicular to the first direction is the same.
15. The semiconductor integrated circuit device according to claim 12 , wherein
the first and second standard cells
have the same positional relationship of vias that are connected to a plurality of terminal wirings which become an input terminal and an output terminal.
16. The semiconductor integrated circuit device according to claim 12 , wherein
in the first and second standard cells,
a plurality of terminal wirings that become an input terminal and an output terminal are extended to a first direction, and a positional relationship of the plurality of terminal wirings in a second direction perpendicular to the first direction is the same.