Method of manufacturing semiconductor device
A method of manufacturing a semiconductor device includes forming a first interconnection and a second interconnection above a semiconductor substrate, forming a first sidewall insulating film on a side wall of the first interconnection, and a second sidewall insulating film on a side wall of the second interconnection, forming a conductive film above the semiconductor substrate with the first interconnection, the first sidewall insulating film, the second interconnection and the second sidewall insulating film formed on, and selectively removing the conductive film above the first interconnection and the second interconnection to form in a region between the first interconnection and the second interconnection a third interconnection formed of the conductive film and spaced from the first interconnection and the second interconnection by the first sidewall insulating film and the second sidewall insulating film.
1. A method of manufacturing a semiconductor device comprising:
forming a first interconnection and a second interconnection above a semiconductor substrate;
forming a first sidewall insulating film on a side wall of the first interconnection, and a second sidewall insulating film on a side wall of the second interconnection;
forming a conductive film above the semiconductor substrate with the first interconnection, the first sidewall insulating film, the second interconnection and the second sidewall insulating film formed on; and
selectively removing the conductive film above the first interconnection and the second interconnection forming in a region between the first interconnection and the second interconnection a third interconnection formed of the conductive film and spaced from the first interconnection and the second interconnection by the first sidewall insulating film and the second sidewall insulating film.
2. The method of manufacturing a semiconductor device according to claim 1 , wherein
selectively removing the conductive film above the first interconnection and the second interconnection includes planarizing the conductive film and etching back the planarized conductive film.
3. The method of manufacturing a semiconductor device according to claim 1 , further comprising, after forming the third interconnection:
patterning the third interconnection to be left between the first interconnection and the second interconnection.
4. The method of manufacturing a semiconductor device according to claim 3 , further comprising, after forming the third interconnection and before patterning the third interconnection:
forming a sacrificial film above the third interconnection; and
planarizing the surface of the sacrificial film, wherein
in patterning the third interconnection, the third interconnection is etched with the sacrificial film as the mask.
5. The method of manufacturing a semiconductor device according to claim 1 , wherein
the first sidewall insulating film includes a first insulating portion formed on the side wall of the first interconnection, and a second insulating portion formed on the first insulating portion, and
the second sidewall insulating film includes a third insulating portion formed on the side wall of the second interconnection, and a fourth insulating portion formed on the third insulating portion.
6. The method of manufacturing a semiconductor device according to claim 5 , further comprising, after forming a third interconnection:
removing the second insulating portion of the first sidewall insulating film, and the fourth insulating portion of the second sidewall insulating film.
7. The method of manufacturing a semiconductor device according to claim 1 , wherein
the first interconnection and the second interconnection are arranged in parallel with each other.
8. The method of manufacturing a semiconductor device according to claim 1 , wherein
the first interconnection and the second interconnection are a gate electrode, and
the third interconnection is an interconnection interconnecting active regions formed on the semiconductor substrate or a lead-out line from an active region of the semiconductor substrate.