Virtualization in a multi-core processor (MCP)
View Patent ↗This invention describes an apparatus, computer architecture, method, operating system, compiler, and application program products for MPEs as well as virtualization in a symmetric MCP. The disclosure is applied to a generic microprocessor architecture with a set (e.g., one or more) of controlling elements (e.g., MPEs) and a set of groups of sub-processing elements (e.g., SPEs). Under this arrangement, MPEs and SPEs are organized in a way that a smaller number MPEs control the behavior of a group of SPEs. The apparatus enables virtualized control threads within MPEs to be assigned to different groups of SPEs for controlling the same. The apparatus further includes a MCP coupled to a power supply coupled with cores to provide a supply voltage to each core (or core group) and controlling-digital elements and multiple instances of sub-processing elements.
1. A multi-core processor, comprising:
a set of main processing elements each comprising a set of virtualized control threads; and
a plurality of groups of sub-processing elements associated with each of the set of main processing elements, each group of sub-processing elements of the plurality of groups of sub-processing elements receiving an independent supply voltage and an independent virtualized control thread to independently adjust the independent supply voltage and a clock frequency of the group of sub-processing elements based on computational requirements of a workload forwarded from a main processing element of the set of main processing elements to the group of sub-processing elements and receiving a second independent supply voltage and a second independent virtualized control thread to independently readjust the independent supply voltage and the clock frequency of the group of sub-processing elements based on different computational requirements of a second workload forwarded from the main processing element to the group of sub-processing elements.
2. The multi-core processor of claim 1 , each of the plurality of groups of sub-processing elements comprising a plurality of sub-processing elements.
3. The multi-core processor of claim 1 , the set of virtualized control threads being configured to send program code and data to the plurality of groups of sub-processing elements.
4. The multi-core processor of claim 3 , the set of virtualized control threads being further configured to collect computation results from the plurality of groups of sub-processing elements.
5. The multi-core processor of claim 1 , the set of virtualized control threads controlling a clock speed, power consumption and computation loading of the plurality of groups of sub-processing elements.
6. The multi-core processor of claim 1 , the set of virtualized control threads being configured to send and receive power control requests between the set of main processing elements and the plurality of groups of sub-processing elements.
7. The multi-core processor of claim 1 , the set of main processing elements comprising a plurality of main processing elements.
8. The multi-core processor of claim 1 , each independent virtualized control thread being associated with a single group of sub-processing elements.
9. A processing system, comprising:
a main processing element;
a group of sub-processing elements; and
a virtualized control thread associating each of the main processing elements with the associated group of sub-processing elements, the virtualized control thread being independent from any other virtualized control thread to enable independent controlling of the group of sub-processing elements, wherein each group of sub-processing elements of the plurality of groups of sub-processing elements receives an independent supply voltage, which is controlled by an associated control thread, by adjusting a power supply and a clock frequency to the group of sub-processing elements based on computational requirements of a workload forwarded from a main processing element of the set of main processing elements to the group of sub-processing elements and receiving a second independent supply voltage and a second independent virtualized control thread to independently readjust the independent supply voltage and the clock frequency of the group of sub-processing elements based on different computational requirements of a second workload forwarded from the main processing element to the group of sub-processing elements.
10. The processing system of claim 9 , the virtualized control thread being embodied within the set of main processing elements.
11. The processing system of claim 9 , the virtualized control thread being configured to send program code and data to the group of sub-processing elements.
12. The processing system of claim 9 , the virtualized control thread being further configured to collect computation results from the group of sub-processing elements.
13. The processing system of claim 9 , the virtualized control thread controlling a clock speed, power consumption and computation loading of the group of sub-processing elements.
14. A processing method, comprising:
associating a set of main processing elements with a set of groups of sub-processing elements using a set of independent virtualized control threads, wherein each group of sub-processing elements of the plurality of groups of sub-processing elements receives an independent supply voltage, which is controlled by an associated control thread, by adjusting a power supply and a clock frequency to the group of sub-processing elements based on computational requirements of a workload forwarded from a main processing element of the set of main processing elements to the group of sub-processing elements and receiving a second independent supply voltage and a second independent virtualized control thread to independently readjust the independent supply voltage and the clock frequency of the group of sub-processing elements based on different computational requirements of a second workload forwarded from the main processing element to the group of sub-processing elements; and
independently controlling each of the set of groups of sub-processing elements using the set of independent virtualized control threads.
15. The processing method of claim 14 , further comprising sending program code and data to the set of groups of sub-processing elements via the set of virtualized control threads.
16. The processing method of claim 14 , further comprising receiving computation results from the set of groups of sub-processing elements via the set of virtualized control threads.
17. The processing method of claim 14 , the controlling comprising controlling a clock speed, a power consumption and a computation loading of the set of groups of sub-processing elements.
18. The processing method of claim 14 , the set of virtualized control threads being embodied as program code within the set of main processing elements.
19. The processing method of claim 14 , the set of main processing elements, the set of groups of sub-processing elements, and the set of virtualized control threads comprising a multi-core processor.
20. A method for deploying a processing system, comprising:
providing a multi-core processor comprising:
a set of main processing elements each comprising a set of virtualized control threads; and
a plurality of groups of sub-processing elements associated with each of the set of main processing elements, each group of sub-processing elements of the plurality of groups of sub-processing elements receiving an independent supply voltage and an independent virtualized control thread to independently adjust the independent supply voltage and a clock frequency of the group of sub-processing elements based on computational requirements of a workload forwarded from a main processing element of the set of main processing elements to the group of sub-processing elements and receiving a second independent supply voltage and a second independent virtualized control thread to independently readjust the independent supply voltage and the clock frequency of the group of sub-processing elements based on different computational requirements of a second workload forwarded from the main processing element to the group of sub-processing elements.