IP Library Granted Patent US 9,113,227
Granted Patent B2
US 9,113,227 · App. 13/564,397 · Granted Aug 18, 2015

Reduced complexity transcoding

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Quick Facts
Patent No.
US 9,113,227
App. No.
13/564,397
Granted
Aug 18, 2015
Kind
B2
Abstract

Efficient transcoding and decoding techniques are widely applicable across multiple different transcoding formats. The techniques find many applications in, as one example, high speed networking. The techniques provide reduced computational and implementation complexity. The techniques may also improve the processing latency compared with other transcoding techniques.

Claims (48)

1. A device comprising:

an input buffer operable to receive input data comprising a control block and a data block, the control block comprising multiple header bits and remaining data, the data block comprising multiple data block bits;

transcoding circuit in communication with the input buffer, the transcoding circuitry operable to obtain transcoded data by swapping the multiple header bits with the multiple data block bits while retaining in place the remaining data of the control block; and an output buffer operable to store the transcoded data.

2. The device of claim 1 , where the transcoding circuitry is operable to add a control field pattern to the multiple header bits.

3. The device of claim 2 , where the control field pattern comprises a position field.

4. The device of claim 2 , where the control field pattern comprises a control block type field.

5. The device of claim 2 , where the control field pattern comprises a continuation field.

6. The device of claim 2 , where:

the control block comprises a first control block, the multiple header bits comprise a first header field of the first control block, and the remaining data comprises first remaining data of the first control block;

the input data further comprises a second control block with a second header field and second remaining data; and where transcoding circuitry is operable to: move the first header field and second header field into a first block-by-block sequence of header data in the transcoded data.

7. The device of claim 6 , where the transcoding circuitry is further operable to:

retain in place the first remaining data and the second remaining data.

8. The device of claim 2 , where:

the control block comprises a first control block and the multiple header bits a first header byte;

the input data further comprises a second control block with a second header byte; and where transcoding circuitry is operable to:

move the first header byte and second header byte into a byte-by-byte sequence of header bytes in the transcoded data.

9. The device of claim 8 , where the transcoding circuitry is further operable to:

retain in place the first remaining data and the second remaining data.

10. The device of claim 1 , where the transcoding circuitry is further configured to: obtain a selected data grouping from selected data blocks within the input data; and insert the selected data grouping into the transcoded data after the multiple header bits.

11. A device comprising:

an input buffer comprising input data in multiple data blocks;

an output buffer; and

transcoding circuitry in communication with the input buffer and the output buffer, the transcoding configured to:

identity, in the input data, a control block comprising a first group of header bits;

reduce the first group of header bits to fewer bits than were originally present in the control block;

add and extended header to transcoded data in the output buffer by swapping a second group of header bits with multiple data block bits of one of the multiple data blocks;

obtain a selected data grouping across selected data blocks in the input data, the selected data blocks comprising the selected data grouping and remaining data;

insert, into the transcoded data, the selected data grouping as a sequential group after the extended header; and

insert, into the transcoded data, the remaining data in accord with an ordering of the remaining data in the input data.

12. The device of claim 11 , where the transcoding circuitry is further operable to specify in the extended header which of the data in the sequential group comprises control block data.

13. The device of claim 11 , where the selected data grouping comprises a selection of data down a column in the input data across the data blocks.

14. The device of claim 13 , where the column comprises a first column in the input data, and includes the first group of header bits reduced to fewer bits.

15. A method for transcoding comprising:

receiving, in an input buffer, input data comprising a control block and a data block, the control block comprising a first group of bits and a second group of bits, the data block comprising a third group of bits and a fourth group of bits;

transcoding the input data to obtain transcoded data by swapping the first group of bits with the third group of bits while retaining in place the second group of bits in the control block and while retaining in place the fourth group of bits of the data block; and saving the transcoded data in an output buffer.

16. The method of claim 15 , where transcoding further comprises:

creating an initial-byte block-by-block sequence of header bytes from control blocks in the input data.

17. The method of claim 16 , where:

the first group of bits comprise a first header byte of the control block;

the input data further comprises another control block with a second header byte and a third byte; and

the method further comprises moving the first header byte and second header byte into the initial-byte block-by-block sequence of header bytes.

18. The method of claim 15 , where transcoding further comprises:

creating a byte-by-byte sequence of header bytes from control blocks in the input data.

19. The method of claim 18 , where:

the first group of bits comprise a first header byte of the control block;

the input data further comprises another control block with a second header byte and a third byte; and

the method further comprises moving the first header byte and second header byte into the byte-by-byte sequence of header bytes.

20. The method of claim 15 , further comprising: obtaining a selected data grouping from selected data blocks within the input data; and inserting the selected data grouping into the transcoded data after the third group of bits.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE PATENT NUMBER 9,385,856 TO 9,385,756 PREVIOUSLY RECORDED AT REEL: 47349 FRAME: 001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 22, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 051144/0648 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE PREVIOUSLY RECORDED ON REEL 047229 FRAME 0408. ASSIGNOR(S) HEREBY CONFIRMS THE THE EFFECTIVE DATE IS 09/05/2018. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047349/0001 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047229/0408 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 1, 2012
From: WANG, ZHONGFENG
To: BROADCOM CORPORATION
Reel/Frame 028701/0241 →