IP Library Granted Patent US 9,240,960
Granted Patent B2
US 9,240,960 · App. 13/564,985 · Granted Jan 19, 2016

Port scheduling for a network device

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Quick Facts
Patent No.
US 9,240,960
App. No.
13/564,985
Granted
Jan 19, 2016
Kind
B2
Abstract

A method and network device provides port scheduling for data ports in the network device. The network device may assign data ports of the network device into port groups according to port characteristics of the data ports. The network device may schedule processing time slots for active data ports by determining a selected port group based on group selection parameters. The network device may then determine a selected data port from the selected port group using port selection criteria. The port selection criteria may maintain minimum and maximum packet spacing requirements for the data ports of a port group. The network device may also maintain an active ports list to disqualify inactive data ports from selection.

Claims (70)

1. A method comprising:

assigning, at scheduling circuitry, data ports of a network device to logical port groups based on a port speed of the data ports;

storing a listing of logical port group assignments for the data ports;

obtaining a selection criterion from memory;

obtaining, at the scheduling circuitry, selection credit values for the logical port groups, the selection credit values and the selection criterion determining a future selection from the logical port groups;

determining, through a group determination process, a selected logical port group from among the logical port groups by determining which of the selection credit values meets the selection criterion; and

after determining the selected logical port group:

determining, through a port determination process separate from the group determination process, a selected data port within the selected logical port group;

obtaining, from the listing of logical port group assignments, identifying information for the selected data port;

allocating, at the scheduling circuitry, a processing time slot to the selected data port; and

responsive to allocating the processing time slot, adjusting a selection credit value for the selected logical port group against consecutive selection.

2. The method of claim 1 , further comprising:

adjusting a selection credit value for a logical port group other than the selected logical port group toward subsequent selection.

3. The method of claim 1 , further comprising:

determining group weights for the logical port groups; and

adjusting the selection credit values as a function of the group weights.

4. The method of claim 1 , further comprising:

determining group weights for the logical port groups other than the selected port group;

determining an adjustment value for the selected logical port group as a function of the group weights; and

adjusting a selection credit value for the selected logical port group by the adjustment value.

5. The method of claim 1 , further comprising:

determining a group weight for a logical port group other than the selected port group, determining an adjustment value for the logical port group other than the selected port group as a function of the group weight; and

adjusting a selection credit value for the logical port group other than the selected port group by the adjustment value.

6. The method of claim 1 , where determining the selected data port comprises:

enforcing a packet spacing requirement.

7. The method of claim 1 , where determining the selected data port comprises:

identifying an active data port within the selected logical port group as an eligible port for the processing time slot; and

identifying an inactive data port within the selected logical port group as an ineligible port for the processing time slot.

8. A device comprising:

input data ports that receive packet data; and

memory configured to store a selection criterion;

scheduling circuitry configured to:

assign the input data ports to logical port groups based on a port speed of the input data ports;

store a listing of logical port group assignments for the data ports;

obtain, from the memory, the selection criterion;

obtain selection credit values for the logical port groups, the selection credit values and the selection criterion determining a future selection from the logical port groups;

determine, through a group determination process, a selected logical port group from among the logical port groups by determining which of the selection credit values meets the selection criterion; and

after determining the selected logical port group:

determine, through a port determination process separate from the group determination process, a selected input data port within the selected logical port group;

obtain, from the listing of logical port group assignments, identifying information for the selected data port;

allocate a processing time slot to the selected input data port; and

responsive to allocating the processing time slot, adjust a selection credit value for the selected logical port group against consecutive selection.

9. The device of claim 8 , wherein the scheduling circuitry is further configured to:

determine group weights for the logical port groups; and

adjust a selection credit value as a function of the group weights.

10. A product comprising:

a computer readable device other than a transitory signal, the computer readable device storing instructions that, when executed by a processor, cause the processor to:

assign data ports of a network device to logical port groups based on a port speed of the data ports;

store a listing of logical port group assignments for the data ports;

obtain, from memory, a selection criterion;

obtain selection credit values for the logical port groups, the selection credit values and the selection criterion determining a future selection from the logical port groups;

determine, through a group determination process, a selected logical port group from among the logical port groups by determining which of the selection credit values meets the selection criterion; and

after determining the selected logical port group:

determine, through a port determination process separate from the group determination process, a selected data port within the selected logical port group; and

obtain, from the listing of logical port group assignments, identifying information for the selected data port;

allocate a processing time slot to the selected data port; and

responsive to allocating the processing time slot, adjusting a selection credit value for the selected logical port group against consecutive selection.

11. The product of claim 10 , wherein the instructions further cause the processor to:

determine a group weight for the logical port groups; and

adjust a selection credit value as a function of the group weights.

12. The product of claim 10 , where the instructions cause the processor to determine the selected data port by enforcing a packet spacing requirement.

13. The product of claim 10 , where the instructions cause the processor to:

identify an active data port within the selected logical port group as an eligible port for the processing time slot; and

identify an inactive data port within the selected port logical group as an ineligible port for the processing time slot.

14. The device of claim 8 , wherein the scheduling circuitry is configured to:

identify an active data port within the selected logical port group as an eligible port for the processing time slot; and

identify an inactive data port within the selected port logical group as an ineligible port for the processing time slot.

15. The method of claim 1 , where storing a listing comprises storing a bit map, the bit map configured to identify a storage location for data for the selected port group.

16. The device of claim 8 , where the port determination process comprises round robin selection.

17. The product of claim 10 , where the port determination process comprises round robin selection.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE PATENT NUMBER 9,385,856 TO 9,385,756 PREVIOUSLY RECORDED AT REEL: 47349 FRAME: 001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 22, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 051144/0648 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE PREVIOUSLY RECORDED ON REEL 047229 FRAME 0408. ASSIGNOR(S) HEREBY CONFIRMS THE THE EFFECTIVE DATE IS 09/05/2018. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047349/0001 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047229/0408 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 2, 2012
From: LAU, MICHAEL; HILL, NATHAN SHUMWAY
To: BROADCOM CORPORATION
Reel/Frame 028709/0102 →