ESD/antenna diodes for through-silicon vias

1. A method for fabricating an integrated circuit, comprising the steps of:

providing a semiconductor substrate;

forming a TSV passing through the substrate, the substrate having an exclusion zone laterally adjacent to the TSV;

forming first, second and third diffusion regions simultaneously in the substrate, the first diffusion region being disposed at least partially within the exclusion zone and the second and third diffusion regions being disposed outside the exclusion zone, the first, second and third diffusion regions being doped to exhibit a first conductivity type, the substrate in at least a region adjacent to the first region being doped to exhibit a second conductivity type opposite the first conductivity type;

forming a gate dielectric over the substrate and a gate conductor over the gate dielectric, the second and third diffusion regions, the gate conductor and the gate dielectric all forming parts of a transistor; and

forming an M1 layer conductor interconnecting the TSV, the first diffusion region, and the gate conductor.

2. The method according to claim 1 , wherein the first region is disposed entirely within the exclusion zone.

3. The method according to claim 1 , further comprising the steps of:

forming a dielectric layer over the substrate; and

prior to the step of forming the M1 layer, etching vias simultaneously through the dielectric layer for the M1 layer conductor to connect to the TSV, the first diffusion region, and the gate conductor.

4. A method for fabricating an integrated circuit, comprising the steps of:

providing a semiconductor substrate;

forming a TSV passing through the substrate;

forming first, second and third diffusion regions simultaneously in the substrate, the first diffusion region being disposed at least partially within 0.5 micron from the TSV and the second and third diffusion regions being disposed entirely beyond 0.5 microns from the TSV, the first, second and third diffusion regions being doped to exhibit a first conductivity type, the substrate in at least a region adjacent to the first region being doped to exhibit a second conductivity type opposite the first conductivity type;

forming a gate dielectric over the substrate and a gate conductor over the gate dielectric, the second and third diffusion regions, the gate conductor and the gate dielectric all forming parts of a transistor; and

forming an M1 layer conductor interconnecting the TSV, the first diffusion region, and the gate conductor.

5. The method according to claim 4 , further comprising the steps of:

forming a dielectric layer over the substrate; and

prior to the step of forming the M1 layer, etching vias simultaneously through the dielectric layer for the M1 layer conductor to connect to the TSV, the first diffusion region, and the gate conductor.

6. The method according to claim 4 , wherein the first region is disposed entirely within 0.5 micron from the TSV.

7. A method for fabricating an integrated circuit, comprising the steps of:

providing a semiconductor substrate;

forming a TSV passing through the substrate;

forming first, second and third diffusion regions simultaneously in the substrate, the first diffusion region surrounding the TSV laterally, the first, second and third diffusion regions being doped to exhibit a first conductivity type, the substrate in at least a region adjacent to the first region being doped to exhibit a second conductivity type opposite the first conductivity type;

forming a gate dielectric over the substrate and a gate conductor over the gate dielectric, the second and third diffusion regions, the gate conductor and the gate dielectric all forming parts of a transistor; and

forming an M1 layer conductor interconnecting the TSV, the first diffusion region, and the gate conductor.

8. The method according to claim 7 , further comprising the steps of:

forming a dielectric layer over the substrate; and

prior to the step of forming the M1 layer, etching vias simultaneously through the dielectric layer for the M1 layer conductor to connect to the TSV, the first diffusion region, and the gate conductor.

9. A method for fabricating an integrated circuit, comprising the steps of:

providing a semiconductor substrate;

forming a TSV passing through the substrate;

forming a plurality of transistors on the substrate, each having first and second diffusion regions, a gate dielectric and a gate conductor overlying the gate dielectric, the plurality of transistors including a particular transistor having a particular diffusion region, a particular gate dielectric and a particular gate conductor overlying the particular gate dielectric;

forming a subject region distinct from all the diffusion regions of all the transistors on the substrate, the subject region being doped to exhibit a first conductivity type, the substrate in at least a second region adjacent to the subject region being doped to exhibit a second conductivity type opposite the first conductivity type, the subject region and the particular diffusion region being formed simultaneously; and

forming an M1 layer conductor interconnecting the TSV, the subject region, and the particular gate conductor,

wherein the point of the subject region which is nearest the TSV is closer to the TSV than the nearest point to the TSV of all of the diffusion regions of all of the transistors on the substrate.

10. The method according to claim 9 , wherein the entire subject region is closer to the TSV than the nearest point to the TSV of the diffusion regions of all of the transistors on the substrate.

11. The method according to claim 9 , wherein the subject region is disposed at least partly within 0.5 microns from the TSV.

12. The method according to claim 9 , wherein the TSV has an associated exclusion zone,

and wherein the subject region is disposed at least partly within the exclusion zone.

13. The method according to claim 12 , further comprising:

a plurality of antenna diodes in the substrate, each connected to one or more of the gate conductors of transistors in the plurality of transistors, each antenna diode in the substrate occupying a respective lateral area in the substrate;

wherein the subject region occupies a lateral area which is larger than the average area occupied laterally by each antenna diode in the substrate which is not connected to a TSV.

14. The method according to claim 13 , wherein the subject region occupies a lateral area which is larger than the area occupied laterally by each antenna diode in the substrate which is not connected to a TSV.

15. The method according to claim 9 , further comprising the steps of:

forming a dielectric layer over the substrate; and

prior to the step of forming the M1 layer, etching vias simultaneously through the dielectric layer for the M1 layer conductor to connect to the TSV, the subject diffusion region, and the particular gate conductor.