High-efficiency, low-power power supply circuit

1. A circuit for charging a capacitor, wherein the capacitor has a first lead coupled to an output voltage V O node, and wherein the capacitor has a second lead coupled to a GND node, the circuit comprising:

a full wave bridge rectifier that supplies a rectified voltage signal (V R ) onto a V R node, and that supplies a ground potential GND onto the GND node; and

a charging circuit that: 1) decouples the V O node from the V R node when V R is greater than a first predetermined voltage V P and, 2) supplies a charging current (I CHARGE ) from the V R node and onto the V O node when V R is less than V P provided that V O is less than a second predetermined voltage V O(MAX) and provided that V R is greater than V O , wherein the second predetermined voltage V O(MAX) is determined by a Zener voltage of a Zener diode and a source-to-gate voltage of a depletion mode field effect transistor (dep-FET).

2. The circuit of claim 1 , wherein the charging circuit comprises:

a zener diode, and wherein the zener diode determines the second predetermined voltage V O(MAX) of the output voltage signal V O .

3. The circuit of claim 1 , wherein the charging circuit comprises:

a switch through which I CHARGE flows from the V R node to the V O node; and

a zener diode that determines the second predetermined voltage V O(MAX) of the output voltage signal V O .

4. The circuit of claim 3 , wherein the switch is a field effect transistor, and wherein the zener diode is coupled via a resistor to a gate of the switch.

5. The circuit of claim 3 , wherein the switch is a depletion mode field effect transistor (dep-FET).

6. The circuit of claim 1 , wherein the V R signal has a maximum value V R(MAX) of more than approximately +150 volts, and wherein V R has a minimum value V R(MIN) that is greater than zero volts.

7. The circuit of claim 1 , wherein there is less than approximately 0.5 microfarads of capacitance on the V R node.

8. The circuit of claim 1 , wherein the charging circuit supplies I CHARGE onto the V O node through a depletion mode field effect transistor (dep-FET), wherein the dep-FET has a body diode, and wherein a cathode of the body diode is coupled to the V R node.

9. The circuit of claim 1 , wherein the charging circuit comprises:

a depletion mode field effect transistor (dep-FET) through which the I CHARGE flows from the V R node to the V O node; and

a voltage detector circuit that detects when V R is greater than the first predetermined voltage V P and that causes the dep-FET to be turned off when V R is greater than the first predetermined voltage V P .

10. The circuit of claim 9 , wherein the voltage detector circuit comprises:

a reference voltage generator;

a comparator having a first input lead, a second input lead, and an output lead, wherein the first input lead of the comparator is coupled via a voltage divider to the V R node, and wherein the second input lead of the comparator is coupled to receive a reference voltage from the reference voltage generator; and

a switch that receives a control signal from the output lead of the comparator, wherein when the switch is on a current can flow from the gate of the dep-FET to the GND node through the switch.

11. The circuit of claim 1 , wherein the charging circuit comprises a comparator, wherein the comparator has a supply voltage input lead, and wherein the supply voltage input lead is coupled to the V R node so that the comparator is powered by the V R node.

12. The circuit of claim 1 , wherein the circuit is a power supply integrated circuit, the circuit further comprising:

a first AC input terminal that is coupled to a first lead of the full wave bridge rectifier;

a second AC input terminal that is coupled to a second lead of the full wave bridge rectifier;

a third terminal that is coupled to and is a part of the GND node; and

a fourth terminal that is coupled to and is a part of the V O node, wherein the first, second, third and fourth terminals are terminals of the power supply integrated circuit.

13. The circuit of claim 1 , wherein the circuit is a packaged integrated circuit device, wherein the capacitor is a part of the packaged integrated circuit device, the circuit further comprising:

a first AC input terminal that is coupled to a first lead of the full wave bridge rectifier;

a second AC input terminal that is coupled to a second lead of the full wave bridge rectifier;

a third terminal that is coupled to and is a part of the GND node; and

a fourth terminal that is coupled to and is a part of the V O node, wherein the first, second, third and fourth terminals are terminals of the packaged integrated circuit device.

14. The circuit of claim 13 , wherein the full wave bridge rectifier and the charging circuit are parts of a first integrated circuit, the circuit further comprising:

a second integrated circuit that is a part of the packaged integrated circuit device, wherein a supply voltage input terminal of the second integrated circuit is coupled to the fourth terminal, and wherein a ground terminal of the second integrated circuit is coupled to the third terminal.

15. The circuit of claim 1 , wherein the charging current supplied from the V R node and onto the V O node is a substantially constant charging current.

16. A method comprising:

(a) using a full wave bridge rectifier to rectify AC voltage signals and thereby generating a full wave rectified signal V R , wherein V R is present on a V R node, and wherein V R is a periodic signal and has a cycle, and wherein V R is at times during the cycle greater than a predetermined voltage V P and at other times during the cycle is less than the predetermined voltage V P ;

(b) providing a capacitor between an output voltage V O node and a ground potential GND node;

(c) if V R has a voltage greater than V P then decoupling the V R node from the output voltage V O node; and

(d) if V R has a voltage less than the V P then supplying a substantially constant charging current from the V R node and onto the V O node provided that a magnitude of a voltage signal V O on the V O node is below a second predetermined voltage and provided that a magnitude of V R is greater than the magnitude of V O on the V O node, wherein the second predetermined voltage is determined by a Zener voltage of a Zener diode and a source-to-gate voltage of a depletion mode field effect transistor (dep-FET).

17. The method of claim 16 , wherein in (d) the substantially constant charging current flows from the V R node, through a depletion mode field effect transistor, and to the V O node.

18. A circuit for charging a capacitor, wherein the capacitor has a first lead coupled to an output voltage V O node, and wherein the capacitor has a second lead coupled to a GND node, the circuit comprising:

a rectifier that supplies a rectified voltage signal (V R ) onto a V R node; and

means for decoupling the V O node from the V R node when V R is greater than a first predetermined voltage V P such that no current flows from the V R node to the V O node, and wherein the means is also for supplying a charging current (I CHARGE ) from the V R node and onto the V O node when V R is less than V P provided that V O is less than a second predetermined voltage V O(MAX) and provided that V R is greater than V O , wherein the second predetermined voltage V O(MAX) is determined by a Zener voltage of a Zener diode and a source-to-gate voltage of a depletion mode field effect transistor (dep-FET).

19. The circuit of claim 18 , wherein the means comprises a depletion mode field effect transistor through which the charging current flows.

20. The circuit of claim 18 , wherein the means comprises a switch through which the charging current flows, and wherein the means further comprises a voltage detector circuit that controls the switch to be open when V R is greater than V P .