Startup circuit detecting stable system clock
View Patent ↗A startup circuit is disclosed operable to perform a startup operation for an electronic device comprising digital circuitry. The startup circuit comprises a first clock generator operable to generate a first clock comprising a first period, and a second clock generator operable to generate a second clock independent of the first clock. The second clock is operable to clock the digital circuitry and comprises a second period less than the first period. A first counter counts a first number of the second periods over the first period, and the second clock is enabled to clock the digital circuitry in response to the first counter.
1. A startup circuit operable to perform a startup operation for an electronic device comprising digital circuitry, the startup circuit comprising:
a first clock generator operable to generate a first clock comprising a first period;
a second clock generator operable to generate a second clock independent of the first clock, wherein the second clock is operable to clock the digital circuitry and comprises a second period less than the first period;
a first counter operable to count a first number of the second periods over the first period; and
an enable circuit operable to enable the second clock to clock the digital circuitry in response to the first counter.
2. The startup circuit as recited in claim 1 , wherein the enable circuit is operable to enable the second clock when the first number exceeds a first threshold.
3. The startup circuit as recited in claim 2 , further comprising a second counter operable to count a second number of times the first number exceeds the first threshold, wherein the enable circuit is operable to enable the second clock when the second number exceeds a second threshold.
4. The startup circuit as recited in claim 1 , wherein the first clock generator comprises a timing capacitor.
5. The startup circuit as recited in claim 1 , wherein the second clock generator comprises a crystal resonator.
6. The startup circuit as recited in claim 1 , wherein:
the first clock generator is operable to generate the first clock at different frequencies based on an environmental condition, wherein a frequency distribution for the first clock comprises a first standard deviation; and
the second clock generator is operable to generate the second clock at different frequencies based on the environmental condition, wherein a frequency distribution for the second clock comprises a second standard deviation less than half the first standard deviation.
7. The startup circuit as recited in claim 1 , wherein at a beginning of the startup operation the first clock is operable to begin oscillating substantially sooner than the second clock.
8. A method of performing a startup operation for an electronic device comprising digital circuitry, the method comprising:
generating a first clock comprising a first period;
generating a second clock independent of the first clock, wherein the second clock is operable to clock the digital circuitry and comprises a second period less than the first period;
counting a first number of the second periods over the first period; and
enabling the second clock to clock the digital circuitry in response to the first number.
9. The method as recited in claim 8 , further comprising enabling the second clock when the first number exceeds a first threshold.
10. The method as recited in claim 9 , further comprising counting a second number of times the first number exceeds the first threshold, and enabling the second clock when the second number exceeds a second threshold.
11. The method as recited in claim 8 , wherein:
the first clock generator is operable to generate the first clock at different frequencies based on an environmental condition, wherein a frequency distribution for the first clock comprises a first standard deviation; and
the second clock generator is operable to generate the second clock at different frequencies based on the environmental condition, wherein a frequency distribution for the second clock comprises a second standard deviation less than half the first standard deviation.
12. The method as recited in claim 8 , wherein at a beginning of the startup operation the first clock begins oscillating substantially sooner than the second clock.
13. A data storage device comprising:
a non-volatile memory; and
control circuitry comprising digital circuitry and a startup circuit operable to perform a startup operation for the data storage device, the startup circuit comprising:
a first clock generator operable to generate a first clock comprising a first period;
a second clock generator operable to generate a second clock independent of the first clock, wherein the second clock is operable to clock the digital circuitry and comprises a second period less than the first period;
a first counter for counting a first number of the second periods over the first period; and
an enable circuit operable to enable the second clock to clock the digital circuitry in response to the first counter.
14. The data storage device as recited in claim 13 , wherein the enable circuit is operable to enable the second clock when the first number exceeds a first threshold.
15. The data storage device as recited in claim 14 , further comprising a second counter operable to count a second number of times the first number exceeds the first threshold, wherein the enable circuit is operable to enable the second clock when the second number exceeds a second threshold.
16. The data storage device as recited in claim 13 , wherein the first clock generator comprises a timing capacitor.
17. The data storage device as recited in claim 13 , wherein the second clock generator comprises a crystal resonator.
18. The data storage device as recited in claim 13 , wherein:
the first clock generator is operable to generate the first clock at different frequencies based on an environmental condition, wherein a frequency distribution for the first clock comprises a first standard deviation; and
the second clock generator is operable to generate the second clock at different frequencies based on the environmental condition, wherein a frequency distribution for the second clock comprises a second standard deviation less than half the first standard deviation.
19. The data storage device as recited in claim 13 , wherein at a beginning of the startup operation the first clock is operable to begin oscillating substantially sooner than the second clock.
20. The data storage device as recited in claim 13 , wherein the non-volatile memory comprises a disk.
21. The data storage device as recited in claim 13 , wherein the non-volatile memory comprises a semiconductor memory.