Flash memory device
View Patent ↗A flash memory device is provided. The flash memory device includes a memory cell array and a pre-charge unit. The pre-charge unit, coupled to a plurality of bit lines corresponding with the memory cell array, pre-charges the bit lines to a predetermined voltage during a pre-charge stage. The pre-charge unit includes a voltage stabilizing unit to provide a constant current to the bit lines. Due to the voltage stabilizing unit, in a programming process, the voltage applied to the bit lines which are not related with programming may not drop as a result of current leakage. Therefore, the memory cells except the memory cell to be programmed are kept in cut off state, without a current passing. As a result, interference with the memory cells which are not to be programmed may be effectively avoided and the accuracy of programming may be improved.
1. A flash memory device, comprising:
a memory cell array comprising a plurality of memory cells; and
a pre-charge unit, coupled to a plurality of bit lines corresponding to the memory cells, adapted for pre-charging the plurality of bit lines to a predetermined voltage during a pre-charge stage, and comprising a voltage stabilizing unit, a bias unit and a plurality of adjusting transistors,
wherein the voltage stabilizing unit provides a substantially stable current to each of the bit lines, and comprises a mirror unit and a current source,
wherein each of the adjusting transistors is coupled to a corresponding bit line, and each of the adjusting transistors comprises a first end coupled to the voltage stabilizing unit, a second end coupled to a corresponding bit line and a control end coupled to the bias unit, and the bias unit is adapted for providing a bias voltage necessary to turn on the adjusting transistors,
wherein the mirror unit comprises an input PMOS transistor, and a plurality of mirror PMOS transistors each of which corresponds to one of the adjusting transistors,
wherein the input PMOS transistor comprises a source coupled to a power supply, a drain and a gate which are coupled to each other and coupled to the current source; and
wherein each of the mirror PMOS transistors comprises a source coupled to the power supply, a gate coupled to the gate of the input PMOS transistor and a drain coupled to the first end of a corresponding adjusting transistor.
2. The flash memory device according to claim 1 , wherein the current source provides a current ranging from about 1 μA to about 5 μA.
3. The flash memory device according to claim 1 , wherein the bias unit comprises a first PMOS transistor, a comparator and a divider,
wherein the comparator comprises an in-phase input end coupled to an output end of the divider and an anti-phase input end coupled to a reference voltage, and
wherein the first PMOS transistor comprises a source coupled to a power supply, a gate coupled to an output end of the comparator, and a drain which is coupled to an input end of the divider and acts as an output end of the bias unit.
4. The flash memory device according to claim 3 , wherein the bias unit further comprises a first NMOS transistor, wherein the first NMOS transistor comprises a source coupled to the input end of the comparator, a gate and a drain coupled to each other and coupled to the drain of the first PMOS transistor.
5. The flash memory device according to claim 3 , wherein the divider comprises a first resistance and a second resistance, wherein the first resistance comprises a first end which is coupled to the drain of the first PMOS transistor and acts as the input end of the divider, a second end coupled to a first end of the second resistance, and wherein the second resistance comprises a second end which is grounded and a first end which is coupled to the in-phase input end of the comparator and acts as the output end of the divider.
6. The flash memory device according to claim 1 , wherein the flash memory device is a split-gate memory device.