Interrupt priority management using partition-based priority blocking processor registers
View Patent ↗A method and circuit for a data processing system ( 20 ) provide a processor-based partitioned priority blocking mechanism by storing priority levels and associated partition information in special purpose registers ( 27 - 29 ) located at the processor core ( 26 ) to enable quick and efficient interrupt priority blocking on a partition basis.
1. A method of managing interrupts at a processor, comprising:
receiving at the processor an interrupt package for a first physical interrupt request, where the interrupt package comprises a first priority value and a first partition identifier identifying a first partition; and
processing the interrupt package against one or more partitions running on one or more targeted virtual processors at the processor by comparing the first priority value and first partition identifier against at least a stored priority level and stored partition identifier retrieved from one or more special purpose registers at the processor to determine on a partition basis if the first physical interrupt request is blocked or forwarded to a targeted virtual processor.
2. The method of claim 1 , where the one or more special purpose registers at the processor comprise a first hardware register for storing a stored partition identifier corresponding to a hypervisor running on the processor.
3. The method of claim 2 , where write access to the first hardware register at the processor is restricted to the hypervisor.
4. The method of claim 2 , where the one or more special purpose registers at the processor comprise a second hardware priority blocking register for storing a stored priority level corresponding to the hypervisor.
5. The method of claim 4 , where processing the interrupt package comprises blocking the first physical interrupt request if the first partition identifier does not match the stored partition identifier retrieved from the first hardware register and the first priority value does not exceed the stored priority level retrieved from the second hardware register.
6. The method of claim 4 , where processing the interrupt package comprises signaling the first physical interrupt request to the targeted virtual processor if the first partition identifier does not match the stored partition identifier retrieved from the first hardware register and the first priority value exceeds the stored priority level retrieved from the second hardware register.
7. The method of claim 1 , where the one or more special purpose registers at the processor comprise a first hardware register for storing a stored partition identifier corresponding to an active guest operating system running on the processor.
8. The method of claim 7 , where the one or more special purpose registers comprise a third hardware priority blocking register for storing a stored priority level corresponding to the active guest operating system.
9. The method of claim 8 , where processing the interrupt package comprises blocking the first physical interrupt request if the first partition identifier matches the stored partition identifier retrieved from the first hardware register and the first priority value does not exceed the stored priority level retrieved from the third hardware register.
10. The method of claim 8 , where processing the interrupt package comprises signaling the first physical interrupt request to the targeted virtual processor if the first partition identifier matches the stored partition identifier retrieved from the first hardware register and the first priority value exceeds the stored priority level retrieved from the third hardware register.
11. The method of claim 1 , where receiving the interrupt package for the first physical interrupt request comprises receiving the interrupt package for a prioritized first physical interrupt request from an interrupt controller which does not include any priority blocking circuits.
12. In a data processing system comprising a processor and an interrupt controller, a method comprising:
processing a first plurality of pending partitioned interrupt requests at the interrupt controller to identify and present to the processor a first interrupt package for a first prioritized physical interrupt request that is not blocked, where the first interrupt package comprises a first priority value and a first partition identifier for the first prioritized physical interrupt request;
receiving the first interrupt package at the processor;
comparing the first partition identifier from the first interrupt package to at least a first stored partition identifier stored in a first hardware register at the processor to determine if the first prioritized physical interrupt request is directed to a partition at the processor; and
comparing the first priority value from the first interrupt package to one or more priority level values stored in one or more priority hardware registers at the processor to determine if the first prioritized physical interrupt request is blocked or forwarded to a targeted virtual processor.
13. The method of claim 12 , where comparing the first partition identifier comprises comparing the first partition identifier from the first interrupt package to a guest partition identifier stored in the first hardware register at the processor to determine if the first prioritized physical interrupt request is directed to an active guest partition at the processor.
14. The method of claim 13 , where comparing the first priority value comprises comparing the first priority value from the first interrupt package to a guest priority level value stored in a guest priority hardware register at the processor if the first partition identifier matches the guest partition identifier stored in the first hardware register.
15. The method of claim 13 , where comparing the first priority value comprises comparing the first priority value from the first interrupt package to a hypervisor priority level value stored in a hypervisor priority hardware register at the processor if the first partition identifier does not match any guest partition identifier stored in the first hardware register.
16. The method of claim 12 , further comprising blocking the first prioritized physical interrupt request if the first priority value from the first interrupt package does not exceed a priority level value stored in a priority hardware register corresponding to the first partition identifier from the first interrupt package.
17. The method of claim 12 , further comprising signaling the first prioritized physical interrupt request to a targeted virtual processor corresponding to the first partition identifier from the first interrupt package if the first priority value from the first interrupt package exceeds a priority level value stored in a priority hardware register corresponding to the first partition identifier from the first interrupt package.
18. The method of claim 12 , where comparing the first priority value comprises comparing the first priority value from the first interrupt package simultaneously to first and second priority level values stored, respectively, in a hypervisor priority hardware register and guest priority hardware register at the processor to determine if the first prioritized physical interrupt request is blocked or forwarded to a targeted virtual processor.
19. A data processing system comprising:
a partitioned interrupt controller for processing a plurality of pending partitioned interrupt requests to identify and present prioritized interrupt requests that are not blocked, along with a priority value and a partition identifier for each presented prioritized interrupt request; and
a processor coupled to the partitioned interrupt controller comprising one or more logical partition identifier registers, a hypervisor priority hardware register for storing a hypervisor priority level, and a guest priority hardware register for storing a guest priority level, where the processor is configured to determine if the first prioritized physical interrupt request is blocked or forwarded to a targeted virtual processor by comparing the priority value against the guest priority level if the partition identifier matches against a logical partition identifier retrieved from the one or more logical partition identifier registers, and comparing the priority value against the hypervisor priority level if the partition identifier does not match a logical partition identifier retrieved from the one or more logical partition identifier registers.
20. The data processing system of claim 19 , where a guest operating system at the processor has write access to the guest priority hardware register for controlling blocking conditions for a guest partition without hypervisor intervention.