IP Library Granted Patent US 9,436,626
Granted Patent B2
US 9,436,626 · App. 13/570,874 · Granted Sep 6, 2016

Processor interrupt interface with interrupt partitioning and virtualization enhancements

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Quick Facts
Patent No.
US 9,436,626
App. No.
13/570,874
Granted
Sep 6, 2016
Kind
B2
Abstract

A method and circuit for a data processing system ( 200 ) provide a processor-based partitioned priority blocking mechanism by storing interrupt identifiers, partition identifiers, thread identifiers, and priority levels associated with accepted interrupt requests in special purpose registers ( 35 - 38 ) located at the processor core ( 26 ) to enable quick and efficient interrupt priority blocking on a partition basis.

Claims (51)

1. A method of managing interrupts at a processor, comprising:

receiving at the processor an interrupt package provided by an interrupt controller, where the interrupt package comprises a first interrupt request, an interrupt identifier corresponding to the first interrupt request, a partition identifier identifying a partition at the processor associated with the first interrupt request, a priority value corresponding to the first interrupt request, and a thread identifier identifying a thread at the processor for the first interrupt request; and

processing the interrupt package against one or more partitions running on the processor by comparing the priority value and partition identifier against at least a stored priority level and stored partition identifier retrieved from special purpose registers at the processor to determine on a partition basis if the first interrupt request is blocked or forwarded to a targeted thread identified by the thread identifier.

2. The method of claim 1 , further comprising:

accepting the first interrupt request if the priority value exceeds the stored priority level for a partition running on the processor; and

providing to the interrupt controller an interrupt acknowledge and the interrupt identifier corresponding to the first interrupt request.

3. The method of claim 1 , where the special purpose registers at the processor comprise:

a first hardware register for storing a logical partition identifier corresponding to a partition running on the processor; and

second hardware priority blocking register for storing the priority level corresponding to a partition running on the processor.

4. The method of claim 3 , where write access to the first hardware register at the processor is restricted to the hypervisor.

5. The method of claim 1 , further comprising storing the interrupt identifier and an interrupt vector corresponding to the first interrupt request to the processor in an external proxy register at the processor if the first interrupt request is directed to a hypervisor identified by the partition identifier.

6. The method of claim 1 , further comprising storing the interrupt identifier and an interrupt vector corresponding to the first interrupt request to the processor in a guest external proxy register at the processor if the first interrupt request is directed to a guest partition identified by the partition identifier.

7. The method of claim 1 , where the special purpose registers at the processor comprise:

a first hardware priority blocking register for storing a first priority level corresponding to the hypervisor running on the processor; and

a second hardware priority blocking register for storing a second priority level corresponding to an active guest running on the processor.

8. The method of claim 7 , where processing the interrupt package comprises blocking the first interrupt request if the partition identifier does not match a stored partition identifier retrieved from special purpose registers and the priority value does not exceed the first priority level retrieved from the first hardware priority blocking register.

9. The method of claim 7 , where processing the interrupt package comprises signaling the first interrupt request to the targeted thread identified by the thread identifier if the first identifier does not match a stored partition identifier retrieved from special purpose registers and the priority value exceeds the first priority level retrieved from the first hardware priority blocking register.

10. The method of claim 7 , where processing the interrupt package comprises blocking the first interrupt request if the partition identifier matches a stored partition identifier retrieved from special purpose registers and the priority value does not exceed the second priority level retrieved from the second hardware priority blocking register.

11. The method of claim 7 , where processing the interrupt package comprises signaling the first interrupt request to the targeted thread identified by the thread identifier if the first identifier matches a stored partition identifier retrieved from special purpose registers and the priority value exceeds the second priority level retrieved from the second hardware priority blocking register.

12. The method of claim 1 , further comprising:

storing the interrupt identifier in an external proxy register at the processor upon determining that the first interrupt request is directed to a hypervisor operating system; and

storing interrupt message data, such as an interrupt source error code associated with the first interrupt request, in an external process identification register at the processor upon determining that the first interrupt request is directed to a hypervisor operating system.

13. The method of claim 1 , further comprising:

storing the interrupt identifier in a guest external proxy register at the processor upon determining that the first interrupt request is directed to a guest operating system; and

storing interrupt message data, such as an interrupt source error code associated with the first interrupt request, in a guest external process identification register at the processor upon determining that the first interrupt request is directed to a guest operating system.

14. In a data processing system comprising a processor and an interrupt controller, a method comprising:

processing a first plurality of pending partitioned interrupt requests at the interrupt controller to identify and present to the processor a first interrupt package for a first prioritized physical interrupt request that is not blocked, where the first interrupt package comprises a first interrupt request, a first interrupt identifier corresponding to the first interrupt request, a first partition identifier identifying a partition at the processor associated with the first interrupt request, a first priority value corresponding to the first interrupt request, and a first thread identifier identifying a thread at the processor for the first interrupt request;

sending the first interrupt package from the interrupt controller over a shared interface to the processor;

comparing the first partition identifier from the first interrupt package to at least a first stored partition identifier stored in a first hardware register at the processor to determine if the first prioritized physical interrupt request is directed to a partition at the processor;

processing the first thread identifier from the first interrupt package to route the first prioritized physical interrupt request to a first targeted virtual processor at the processor; and

comparing the first priority value from the first interrupt package to one or more priority level values stored in one or more priority hardware registers at the processor to determine if the first prioritized physical interrupt request is blocked or forwarded by the first targeted virtual processor.

15. The method of claim 14 , where comparing the first partition identifier comprises comparing the first partition identifier from the first interrupt package to a guest partition identifier stored in the first hardware register at the processor to determine if the first prioritized physical interrupt request is directed to an active guest partition at the processor.

16. The method of claim 15 , where comparing the first priority value comprises comparing the first priority value from the first interrupt package to a guest priority level value stored in a guest priority hardware register at the processor if the first partition identifier matches the guest partition identifier stored in the first hardware register.

17. The method of claim 15 , where comparing the first priority value comprises comparing the first priority value from the first interrupt package to a hypervisor priority level value stored in a hypervisor priority hardware register at the processor if the first partition identifier does not match any guest partition identifier stored in the first hardware register.

18. The method of claim 14 , further comprising:

storing the first interrupt identifier in first proxy register at the processor upon determining that the first prioritized physical interrupt request is directed to a hypervisor operating system; and

storing interrupt message data associated with the first interrupt request in a first process identification register at the processor upon determining that the first prioritized physical interrupt request is directed to a hypervisor operating system.

19. The method of claim 1 , further comprising:

storing the first interrupt identifier in a second proxy register at the processor upon determining that the first prioritized physical interrupt request is directed to a guest operating system; and

storing interrupt message data associated with the first interrupt request in a second process identification register at the processor upon determining that the first prioritized physical interrupt request is directed to a guest operating system.

20. A data processing system comprising:

a partitioned interrupt controller for processing a plurality of pending partitioned interrupt requests to identify and present interrupt requests along with interrupt identifiers corresponding to the interrupt requests, a partition identifier identifying partitions associated with each interrupt request, a first priority value corresponding to each interrupt request, and a thread identifier identifying a virtual processor associated with each interrupt request; and

a processor coupled to the partitioned interrupt controller comprising:

one or more logical partition identifier registers;

a hypervisor priority hardware register for storing a hypervisor priority level;

a guest priority hardware register for storing a guest priority level;

an external proxy register for storing interrupt identifier and vector information for interrupts directed to a hypervisor operating system;

a guest external proxy register for storing interrupt identifier and vector information for interrupts directed to a guest operating system;

an external process identifier register for storing interrupt message data for interrupts directed to the hypervisor operating system; and

a guest external process identifier register for storing interrupt message data for interrupts directed to the guest operating system;

where the processor is configured to route the first interrupt request to a targeted virtual processor identified by the first thread identifier and then determine if the first interrupt request is blocked or forwarded by comparing the first priority value against the guest priority level if the first partition identifier matches against a logical partition identifier retrieved from the one or more logical partition identifier registers, and comparing the first priority value against the hypervisor priority level if the first partition identifier does not match a logical partition identifier retrieved from the one or more logical partition identifier registers.

Assignments (23)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 15, 2023
From: NXP USA, INC.
To: EIREOG INNOVATIONS LIMITED
Reel/Frame 065880/0480 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050744/0097 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NATURE OF CONVEYANCE PREVIOUSLY RECORDED AT REEL: 040652 FRAME: 0241. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER AND CHANGE OF NAME. Recorded Jan 5, 2017
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 041260/0850 →
MERGER Recorded Nov 8, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NXP USA, INC.
Reel/Frame 040652/0241 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
SUPPLEMENT TO THE SECURITY AGREEMENT Recorded Jun 16, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037486/0517 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0652 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0614 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0633 →
SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
Reel/Frame 031591/0266 →
SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Apr 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Apr 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Apr 20, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 9, 2012
From: MARIETTA, BRYAN D.; WHISENHUNT, GARY L.; GALA, KUMAR K.; KRAMER, DAVID B.
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 028759/0350 →