IP Library Granted Patent US 8,847,357
Granted Patent B2
US 8,847,357 · App. 13/571,067 · Granted Sep 30, 2014

Opto-electronic device

Inventors: Sukhjiban Dosanjh (Ipswich, GB); Ian Lealman (Ipswich, GB); Gordon Burns (Ipswich, GB); Michael Robertson (Ipswich, GB)
Assignee: The Centre for Intergrated Photonics Limited
H01L29/0607H01S5/2224H01S5/2226H01S5/2206H01L33/145B82Y20/00H01S5/34313H01S5/3434H01S5/2227H01S5/2275H01S5/34306
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Quick Facts
Patent No.
US 8,847,357
App. No.
13/571,067
Granted
Sep 30, 2014
Kind
B2
Abstract

The present invention provides a current blocking structure for electronic devices, preferably optoelectronic devices. The current blocking structure comprises a semiconductor material arrangement comprising an n-type ruthenium doped indium phosphide (Ru—InP) layer and a first p-type semiconductor material layer wherein the n-type Ru—InP layer is less than 0.6 μm thick. The semiconductor material arrangement and p-type semiconductor material layer form a current blocking p-n junction. The current blocking structure may further comprise other n-type layers and/or multiple n-type Ru—InP layers and/or intrinsic/undoped layers wherein the n-type Ru—InP layers may be thicker than 0.6 μm.

Claims (28)

1. An electronic device comprising a current blocking structure; the current blocking structure comprising:

a) a first p-type semiconductor material layer; and,

b) a semiconductor material arrangement comprising an n-type ruthenium doped indium phosphide (Ru—InP) layer;

the semiconductor material arrangement and p-type semiconductor material layer forming a first p-n junction, wherein the n-typed Ru—InP layer is directly disposed over the first p-type semiconductor material layer;

wherein the n-type ruthenium doped indium phosphide layer comprises a thickness less than about 0.6 μm.

2. The device as claimed in claim 1 wherein the semiconductor material arrangement is a layer stack comprising the n-type ruthenium doped indium phosphide layer and one or more further n-type InP materials.

3. The device as claimed in claim 1 wherein the current blocking structure further comprises an intrinsic semiconductor material.

4. The device as claimed in claim 1 further comprising a second p-n junction disposed to a side of the first p-n junction: the second p-n junction comprising an n-type semiconductor material layer and a p-type semiconductor material layer.

5. The device as claimed in claim 4 wherein the n-type ruthenium doped indium phosphide layer and first p-type semiconductor material layer are positioned in a substantially opposite orientation to the n and p-type semiconductor material layers of the second p-n junction.

6. The device as claimed in claim 5 wherein the second p-n junction is bordered by the intrinsic semiconductor material.

7. An electronic device comprising a current blocking structure; the current blocking structure comprising:

a) a first p-type semiconductor material layer;

b) a semiconductor material arrangement comprising an n-type ruthenium doped indium phosphide (Ru—InP) layer;

the semiconductor material arrangement and p-type semiconductor material layer forming a first p-n junction;

wherein the semiconductor material arrangement is a layer stack comprising the n-type ruthenium doped indium phosphide layer and one or more further n-type InP materials;

and a second p-n junction disposed to a side of the first p-n junction: the second p-n junction comprising an n-type semiconductor material layer and a p-type semiconductor material layer.

8. The device as claimed in claim 7 wherein the n-type ruthenium doped indium phosphide layer and first p-type semiconductor material layer are positioned in a substantially opposite orientation to the n and p-type semiconductor material layers of the second p-n junction.

9. An electronic device comprising a current blocking structure; the current blocking structure comprising:

a) a first p-type semiconductor material layer;

b) a semiconductor material arrangement comprising an n-type ruthenium doped indium phosphide (Ru—InP) layer;

the semiconductor material arrangement and p-type semiconductor material layer forming a first p-n junction;

wherein the current blocking structure further comprises an intrinsic semiconductor material; and

a second p-n junction disposed to a side of the first p-n junction: the second p-n junction comprising an n-type semiconductor material layer and a p-type semiconductor material layer.

10. The device as claimed in claim 9 wherein the semiconductor material arrangement is a layer stack comprising the n-type ruthenium doped indium phosphide layer and one or more further n-type InP materials.

11. The device as claimed in claim 9 wherein the n-type ruthenium doped indium phosphide layer and first p-type semiconductor material layer are positioned in a substantially opposite orientation to the n and p-type semiconductor material layers of the second p-n junction.

12. The device as claimed in claim 11 wherein the second p-n junction is bordered by the intrinsic semiconductor material.

13. The device as claimed in claim 9 wherein the ruthenium doped indium phosphide layer comprises a thickness between about 0.1 μm and about 0.4 μm.

14. The device as claimed in claim 9 wherein the current blocking structure comprises a second p-type semiconductor material.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 4, 2017
From: THE CENTRE FOR INTEGRATED PHOTONICS LIMITED
To: HUAWEI TECHNOLOGIES CO., LTD.
Reel/Frame 043476/0096 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 17, 2012
From: DOSANJH, SUKHJIBAN; LEALMAN, IAN; BURNS, GORDON; ROBERTSON, MICHAEL
To: THE CENTRE FOR INTERGRATED PHOTONICS LIMITED
Reel/Frame 029147/0265 →
Priority Claims (1)
GB 1002088.1 · Feb 9, 2010 · national
Continuity (2)
Continuation PCTGB2011050221 · Feb 9, 2011
Related Publication 20130200492A1 · Aug 8, 2013