Method, apparatus, and system for performing time synchronization on PCIE devices
Embodiments of the present invention provide a method, an apparatus, and a system for performing time synchronization on PCIE (PCI Express, peripheral component interconnect express) devices. The method mainly includes: a PCIE device receiving, through a hardware interface, a time synchronization signal sent from a clock source device; parsing, by the PCIE device, the time synchronization signal to obtain clock information carried in the time synchronization signal, and using the clock information as a clock of the PCIE device. The PCIE devices are supported to access a synchronous network, and the PCIE devices are supported to be used as a global clock source.
1. A method for performing time synchronization on a peripheral component interconnect express (PCIE) device, comprising:
receiving, by the PCIE device through a synchronization signal interface, a time synchronization signal sent from a clock source device, wherein the time synchronization signal comprises a 1 pulse per second (1 PPS) signal and a Time Of Date (TOD) signal;
parsing, by the PCIE device, the time synchronization signal to obtain clock information and time signal carried in the time synchronization signal; and
performing, by the PCIE device, the time synchronization according to the clock information and the time signal;
wherein the clock source device comprises a master clock source device and a slave clock source device, and the method further comprises:
replacing, by the PCIE device, the master clock source device with the slave clock source device to send the time synchronization signal, when the master clock source device has a failure or when no time synchronization signal of the master clock source device meets the requirement.
2. The method for performing time synchronization on the PCIE device according to claim 1 , wherein the synchronization signal interface comprises a clock phase discrimination circuit and a TOD communication interface.
3. The method for performing time synchronization on the PCIE device according to claim 1 , wherein the PCIE device through an exclusive chip or a Field-Programmable Gate Array (FPGA), parses the time synchronization signal to extract the clock information and the time signal carried in the time synchronization signal.
4. The method for performing time synchronization on the PCIE device according to claim 1 , wherein the PCIE device is independent from the clock source device.
5. A system for performing time synchronization on a peripheral component interconnect express (PCIE) device, comprising:
a clock source device, configured to send a time synchronization signal to the PCIE device, wherein the clock source device and the PCIE device are independent from each other; and
the PCIE device, comprising a synchronization signal interface, and configured to receive, through the synchronization signal interface, the time synchronization signal sent from the clock source device, parse the time synchronization signal to obtain clock information and time signal carried in the time synchronization signal, and perform the time synchronization according to the clock information and the time signal, wherein the time synchronization signal comprises a 1 pulse per second (1 PPS) signal and a Time Of Date (TOD) signal;
wherein the clock source device comprises a master clock source device and a slave clock source device, and the PCIE device is further configured to replace the master clock source device with the slave clock source device to send the time synchronization signal, when the master clock source device has a failure or when no time synchronization signal of the master clock source device meets the requirement.
6. The system for performing time synchronization on the PCIE device according to claim 5 , wherein the synchronization signal interface comprises a clock phase discrimination circuit and a TOD communication interface.
7. The system for performing time synchronization on the PCIE device according to claim 5 , wherein the PCIE device through an exclusive chip or a Field-Programmable Gate Array (FPGA), parses the time synchronization signal to extract the clock information and the time signal carried in the time synchronization signal.
8. The system for performing time synchronization on the PCIE device according to claim 5 , wherein the clock source device is further configured to parse a received clock signal from an upper-level clock source device or a time synchronization network to obtain time synchronization signal of the PCIE devices.