IP Library Granted Patent US 8,786,745
Granted Patent B2
US 8,786,745 · App. 13/577,162 · Granted Jul 22, 2014

Solid-state image pickup device

Inventors: Shoji Kawahito (Hamamatsu, JP); Keita Yasutomi (Hamamatsu, JP)
Assignee: National University Corporation Shizuoka University
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Quick Facts
Patent No.
US 8,786,745
App. No.
13/577,162
Granted
Jul 22, 2014
Kind
B2
Abstract

In a pixel 11 , a floating semiconductor region FD accumulates a charge from a photoelectric transducer PD. A first charge transfer path CTP 1 extends from the photoelectric transducer PD to the floating semiconductor region FD through the storage diode SD. A second charge transfer path CTP 2 extends from the photoelectric transducer PD to the floating semiconductor region. An output unit AMP provides a signal corresponding to a potential in the floating semiconductor region FD. The first charge transfer path CTP includes a first shutter switch TR(GS 1 ) for controlling a transfer of the charge from the photoelectric transducer PD, the storage diode SD for accumulating the charge from the photoelectric transducer PD, and a transfer switch TR(TF 1 ) for controlling a transfer of the charge from the storage diode SD to the floating semiconductor region PD, while the second charge transfer path CTP includes a shutter switch TR(GS 2 ) for controlling a transfer of the charge from the photoelectric transducer PD.

Claims (41)

1. A solid-state image pickup device comprising:

a pixel array including a plurality of pixels arranged in an array;

a control circuit for generating first, second, and third control signals for controlling the pixel;

a readout circuit for reading the first and second pixel signals from the pixel array in one frame; and

a signal processing unit for processing signals from the readout circuit;

wherein each pixel includes:

a photoelectric transducer for generating an electric signal from light received thereby;

a floating semiconductor region for accumulating a charge from the photoelectric transducer;

a first charge transfer path extending from the photoelectric transducer to the floating semiconductor region;

a second charge transfer path extending from the photoelectric transducer to the floating semiconductor region; and

an output unit for providing a signal corresponding to a potential in the floating semiconductor region;

wherein one of the first and second charge transfer paths includes a first shutter switch for controlling a transfer of the charge from the photoelectric transducer in response to the first control signal, a first storage diode for accumulating the charge from the photoelectric transducer, and a first transfer switch for controlling a transfer of the charge from the first storage diode to the floating semiconductor region in response to the second control signal;

wherein the other of the first and second charge transfer paths includes a second shutter switch for controlling a transfer of the charge from the photoelectric transducer to the floating semiconductor region through no charge storage unit in response to the third control signal;

wherein the first pixel signal corresponds to a first transfer charge transferred to the floating semiconductor region through the first charge transfer path;

wherein the second pixel signal corresponds to a second transfer charge transferred to the floating semiconductor region through the second charge transfer path;

wherein a first accumulation period for accumulating the charge transferred through the one charge transfer path is longer than a second accumulation period for accumulating the charge transferred through the other charge transfer path;

wherein the signal processing unit includes a signal synthesis unit for synthesizing a synthetic image signal from the first and second pixel signals;

wherein the synthetic image signal has a dynamic range wider than that of each of the first and second image signals;

wherein the pixel includes a reset switch for resetting the floating semiconductor region;

wherein the control circuit generates a reset signal for controlling the reset switch;

wherein the first pixel signal includes a first signal level corresponding to the first transfer charge and a first reset level corresponding to a potential of the floating semiconductor region reset by the reset switch;

wherein the second pixel signal includes a second signal level corresponding to the second transfer charge and a second reset level corresponding to a potential of the floating semiconductor region reset by the reset switch; and

wherein the readout circuit includes first and second correlated double sampling circuits for sampling the first and second pixel signals, respectively.

2. A solid-state image pickup device comprising: a pixel array including a plurality of pixels arranged in an array:

a control circuit for generating first, second, and third control signals for controlling the a readout circuit for reading the first and second pixel signals from the pixel array in one frame; and

a signal processing unit for processing signals from the readout circuit; wherein each pixel includes: a photoelectric transducer for generating an electric signal from light received thereby;

a floating semiconductor region for accumulating a charge from the photoelectric transducer;

a first charge transfer path extending from the photoelectric transducer to the floating semiconductor region;

a second charge transfer path extending from the photoelectric transducer to the floating semiconductor region; and

an output unit for providing a signal corresponding to a potential in the floating semiconductor region;

wherein one of the first and second charge transfer paths includes a first shutter switch for controlling a transfer of the charge from the photoelectric transducer in response to the first control signal, a first storage diode for accumulating the charge from the photoelectric transducer, and a first transfer switch for controlling a transfer of the charge from the first storage diode to the floating semiconductor region in response to the second control signal;

wherein the other of the first and second charge transfer paths includes a second shutter switch for controlling a transfer of the charge from the photoelectric transducer to the floating semiconductor region through no charge storage unit in response to the third control signal;

wherein the first pixel signal corresponds to a first transfer charge transferred to the floating semiconductor region through the first charge transfer path;

wherein the second pixel signal corresponds to a second transfer charge transferred to the floating semiconductor region through the second charge transfer path;

wherein a first accumulation period for accumulating the charge transferred through the one charge transfer path is longer than a second accumulation period for accumulating the charge transferred through the other charge transfer path;

wherein the signal processing unit includes a signal synthesis unit for synthesizing a synthetic image signal from the first and second pixel signals

wherein the synthetic image signal has a dynamic range wider than that of each of the first and second image signals;

wherein the pixel further comprises a third charge transfer path extending from the photoelectric transducer to the floating semiconductor region;

wherein the third charge transfer path includes a third shutter switch for controlling a transfer of the charge from the photoelectric transducer in response to a fifth control signal, a third storage diode for accumulating the charge from the photoelectric transducer, and a third transfer switch for controlling a transfer of the charge from the third storage diode to the floating semiconductor region in response to a sixth control signal;

wherein the signal processing unit reads a third pixel signal from the pixel array; and

wherein the third pixel signal corresponds to the charge transferred to the floating semiconductor region through the third charge transfer path.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 5, 2012
From: KAWAHITO, SHOJI; YASUTOMI, KEITA
To: NATIONAL UNIVERSITY CORPORATION SHIZUOKA UNIVERSITY
Reel/Frame 029086/0951 →
Priority Claims (1)
JP P2010-024595 · Feb 5, 2010 · national
Continuity (1)
Related Publication 20130044247A1 · Feb 21, 2013