Clock recovery method and clock recovery arrangement for coherent polarization multiplex receivers
View Patent ↗Component signal values are derived from component signals and fed to at least one fixed equalizer which generates equalizer output signals. The signals are fed to phase error detectors generating phase error signals. The phase error signals are combined with further phase error signals derived by further error detectors receiving signal values from further equalizers and/or the component signal values directly from sample units.
1. A clock recovery method for coherent polarization multiplex receivers, which comprises the steps of:
coherent demodulating a received polarization multiplex signal and deriving orthogonal signal components;
sampling and converting the orthogonal signal components into digital component values;
feeding the digital component values to at least one equalizer;
deriving phase error values from output values of the at least one equalizer, and from output values of the further equalizers or the digital component values;
calculating resulting phase error values from at least two derived phase error values;
deriving an oscillator control signal from the resulting phase error values;
controlling at least one controllable oscillator generating a sample signal for sampling the orthogonal signal components or re-sampling the digital component values and
wherein the calculating resulting phase error values, comprises:
calculating gain coefficients as weighting factors by evaluating performance of
phase error detectors;
calculating weighted phase error values by applying the gain coefficients; and
adding the weighted phase error values to calculate the resulting phase error values.
2. The clock recovery method according to claim 1 , which further comprises:
calculating squared gain coefficients;
adding the squared gain coefficients;
deriving a normalizing factor; and
calculating the resulting phase error values which amplitudes are substantially independent of a polarization mixing angle between received orthogonal optical signals and a polarization beam splitter and differential group delay.
3. The clock recovery method according to claim 2 , which further comprises:
calculating the gain coefficients used as the weighting factors according to
K i [n]√{square root over (X PEIi 2 [n]+X PEQi 2 [n])} (4)
with in-phase error values (X PEIi ) and quadrature-phase error values (X PEQi ), calculated according to
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with n=sample instant; X Ei —output signal of equalizer EQU i .
4. The clock recovery method according to claim 3 , which further comprises generating the phase error values according to:
X PEi [n]=XI Ei [n−½](XI Ei [n]−XI Ei [n−I])+XQ Ei [n−½](XQ E [n]−Q Ei [n−1]), Y PEi [n]=YI Ei [n−½](YI Ei [n]−YI Ei [n−I])+YQ Ei [n−½](YQ Ei [n]−YQ Ei [n−1]), with XI Ei , XQ Ei ; YI Ei /YQ Ei equalizer output values/component signal values; n—sample instant; i=1, 2, . . . , N.
5. The clock recovery method according to claim 1 , which further comprises:
calculating resultant weighted phase error values:
X WPE [n]=Σ i=1 N X WPEi [n] (2);
with X WPEi being the weighted phase error values, calculated according to
X WPEi [n]=K i *X PEi [n] (1)
with Ki being gain coefficients, and calculating the resultant phase error values according to
X RPE [n]=X WP E[n]*K SET /(Σ K i 2 (3)
n=sample instant; i=1, 2, . . . , N; summation I=1, 2, . . . , N; K SET —scaling factor.
6. A clock recovery configuration for a coherent polarization multiplex receiver, the clock recovery configuration comprising:
at least one phase locked loop deriving a sample signal and including:
a sample unit;
a loop filter;
a controllable oscillator connected to said look filter, said contollable oscillator feeding the sample signals into said sample unit; and
a combined phase error detector unit connected to said loop filter and having at least one equalizer receiving sampled component values and outputting equalizer output values, said combined phase error detector unit further having a plurality of phase error detectors receiving equalizer output values or the sampled component values generating phase error values, and having means for combining phase error values to derive resultant error values for controlling said controllable oscillator of said at least one phase locked loop, wherein said means for combining phase error values to derive resultant error values comprises:
gain coefficient estimators receiving the equalizer output values for calculating gain coefficients as weighting factors;
multipliers connected to said gain coefficient estimators and receiving the phase error values and the associated gain coefficients for calculating weighted phase error values; and
a first adder receiving the weighted phase error values and calculating resultant weighted phase error values for controlling said controllable oscillator.
7. The clock recovery configuration according to claim 6 , wherein:
said gain coefficient estimators deriving the gain coefficients representing a performance of said phase error detectors; and
means for deriving the resultant phase error values, which are virtually independent of a polarization mixing angle between received orthogonal signals and a polarization beam splitter, and of a differential group delay.