Scalable construction for lateral semiconductor components having high current-carrying capacity
The invention relates to semiconductor components, in particular to a scalable construction for lateral semiconductor components having high current-carrying capacity. A transistor cell according to the invention comprises a control electrode ( 203 ), a plurality of source fields ( 201 ) and a plurality of drain fields ( 202 ). The control electrode completely encloses at least one of the source fields or drain fields. A transistor according to the invention comprises a plurality of transistor cells on a substrate, each of which comprises a source contact field ( 206 ) and/or a drain contact field ( 207 ). The source contact fields are conductively connected to each other on the other side of the substrate and the drain contact fields are likewise conductively connected to each other on the other side of the substrate. The method according to the invention for producing a transistor comprises the following steps: providing a substrate; forming a plurality of transistor cells on the substrate, each of which comprises a control electrode, a plurality of source fields and a plurality of drain fields; conductively connecting the control electrodes to each other; forming a source contact field and/or a drain contact field in each transistor cell; conductively connecting the source contact fields of each transistor cell to a source contact field; conductively connecting the drain fields of each transistor cell to a drain contact field; forming at least one bump ( 208 ) on each of the source contact fields and on each of the drain contact fields; providing a circuit board; conductively connecting the bumps of the source contact fields to each other by means of conductive tracks on the circuit board; and conductively connecting the bumps of the drain contact fields to each other by means of conductive tracks on the circuit board. The arrangement of the bumps and the conductive tracks on the circuit board makes a low semiconductor surface assignment by wiring possible. The arrangement according to the invention of the source fields, drain fields and control electrodes relative to the bumps makes a low heat resistance possible between the active transistor regions and the bumps.
1. A transistor comprising:
at least a first and a neighboring second transistor cell, each comprising:
a contact field which has at least one bump that is conductively connectable to a circuit board,
a control electrode which makes up a network of concentric and radial metallization with respect to the at least one bump;
a plurality of source fields; and
a plurality of drain fields,
wherein the source fields and the drain fields are concentrically arranged around the contact field,
wherein
the control electrode completely encloses at least one of the source fields and at least one of the drain fields, and
wherein the source fields of the first and the second transistor cell are conductively connected to the contact field of the first transistor cell and the drain fields of the first and the second transistor cell are conductively connected to the contact field of the second transistor cell.
2. A transistor cell according to claim 1 ,
wherein
the concentric metallizations are distanced from each other increasingly with increasing distance from the bump such that the temperature of the control electrode that develops during transistor operation does not increase with increasing distance from the at least one bump.
3. A transistor cell according to claim 1 ,
wherein
the control electrode has a hexagonal arrangement.
4. A transistor cell according to claim 1 ,
wherein
the control electrode has a polygonal arrangement, wherein the number of edges of the polygons is an integral multiple of 4.
5. A transistor according to claim 1 having a plurality of first and neighboring second transistor cells wherein the transistor cells are arranged on a semiconductor surface wherein the bumps of the contact fields of the first transistor cells are connected to each other by connective paths on the circuit board wherein the bumps of the contact fields of the second transistor cells are connected to each other by further connective paths on the circuit board.
6. A transistor according to claim 5 ,
wherein
the transistor cells on the semiconductor surface are laterally fitted together.
7. A transistor according to claim 5 ,
wherein
the control electrodes of the transistor cells are conductively connected to each other on a substrate that is not the substrate on which the source contact fields and the drain contact fields are conductively connected to each other.
8. A method for producing a transistor, comprising:
providing a semiconductor surface;
forming at least a first and a neighboring second transistor cell on the semiconductor surface, each of which comprising a control electrode arranged between a plurality of laterally arranged source fields and a plurality of laterally arranged drain fields; and conductively connecting the control electrodes to each other,
forming a contact field in each transistor cell such that the source fields and the drain fields are arranged concentrically around the contact field;
conductively connecting the source fields of the first and the second transistor cell to the contact field of the first transistor cell such that the first transistor cell comprises a source contact field;
conductively connecting the drain fields of the first and the second transistor cell to the contact field of the second transistor cell such that the second transistor cell comprises a drain contact field;
forming at least one bump on each of the source contact fields and on each of the drain contact fields;
providing a circuit board;
conductively connecting the bumps of the source contact fields to each other by means of conductive tracks on the circuit board; and
conductively connecting the bumps of the drain contact fields to each other by means of further conductive tracks on the circuit board,
wherein,
in each of the transistor cells, the control electrode is formed in such a manner that it completely encloses at least one of the source fields and at least one of the drain fields and wherein,
in each of the transistor cells, the control electrode makes up a network of concentric and radial metallization with respect to the at least one bump.