Time multiplexing at different rates to access different memory types

1. A memory controller, comprising:

clock circuitry configured to provide clock signals having different clock rates for different types of memory devices; and

an interface circuit configured to time division multiplex data destined for the different types of memory devices on a shared signal bus such that the data is output at the different clock rates for the different types of memory devices, the interface circuit also configured to provide first write data at a first one of the clock rates for write operations directed to a first type of memory device of the different types of memory devices, wherein the first type of memory device is configured to transmit and receive over the shared signal bus at the first clock rate and to provide second write data at the first clock rate for write operations directed to a second type of memory device of the different types of memory devices, wherein the second type of memory device is configured to transmit and receive over the shared signal bus at a second one of the clock rates that is slower than the first clock rate, and a portion of the second write data comprises dummy data.

2. The memory controller of claim 1 , wherein the interface circuit is further configured to select different instruction protocols for writing the data to the different types of memory devices based on a mapping that maps the different types of memory devices to the different instruction protocols.

3. The memory controller of claim 1 , wherein:

the clock signals comprise a first clock signal and a second clock signal;

the first clock signal operates at a first native clock rate associated with a first one of the memory device types;

the second clock signal operates at a second native clock rate associated with a second one of the memory device types; and

the first native clock rate is different than the second native clock rate.

4. The memory controller of claim 1 , wherein the first clock rate is an integer multiple of the second clock rate.

5. The memory controller of claim 4 , wherein

the second write data includes data that is repeated over a plurality of consecutive clock cycles at the first clock rate to provide data at the second clock rate.

6. The memory controller of claim 5 , wherein the interface circuit is further configured to:

output the first write data at the first clock rate on the shared signal bus by outputting each instance of the first write data for a single clock cycle based on the first clock rate; and

output the second write data at the second clock rate by outputting data repeated over a plurality of consecutive clock cycles of the first clock rate during a single clock cycle based on the second clock rate.

7. The memory controller of claim 4 , wherein the interface circuit further comprises:

a receiver configured to receive first data sent by the first type of memory device at the first clock rate and to receive second data sent by the second type of memory device at the second clock rate; and

at least one latch configurable to sample the first data at a first clock rate and to sample the second data at the first clock rate.

8. The memory controller of claim 4 , wherein the interface circuit further comprises:

at least one latch configurable to sample first read data at the first clock rate during read operations from the first type of memory device and to sample second read data at the first clock rate during read operations from the second type of memory device, wherein the second read data includes data that is repeated over a plurality of consecutive clock cycles at the first clock rate to provide data at the second clock rate; and

a rate adaptation circuit configured to process the sampled second read data to provide read data that does not include the data that is repeated over a plurality of consecutive clock cycles.

9. The memory controller of claim 1 , further comprising a rate adaptation circuit configured to buffer the second write data at the first clock rate and read out the buffered data at the second clock rate to provide write data at the second clock rate for the shared signal bus, wherein the write data at the second clock rate does not include the dummy data.

10. The memory controller of claim 1 , wherein the interface circuit is further configured to time multiplex the data with control information destined for the different types of memory devices over the shared signal bus.

11. The memory controller of claim 1 , wherein:

the shared signal bus comprises a shared data bus; and

the interface circuit is further configured to send control information to the different types of memory devices on a shared control bus in a time division multiplexed manner.

12. The memory controller of claim 11 , wherein the interface circuit is further configured to:

send control information to a first type of memory device of the different types of memory devices at a first rate; and

send control information to a second type of memory device of the different types of memory devices at a second rate that is different than the first rate.

13. The memory controller of claim 1 , further comprising device selection logic configured to select, for a given data transfer:

one of the different types of memory devices as a target memory device; and

one of the different clock rates based on a mapping of the different types of memory devices to the different clock rates.

14. The memory controller of claim 13 , wherein the clock circuitry comprises a switch configured to provide one of the clock signals for the given data transfer by selecting, based on a signal from the device selection logic, one of a plurality of signals, each of which has a different frequency.

15. The memory controller of claim 1 , wherein the interface circuit is further configured to use a signal path of the signal bus to:

send data to a first memory type of the different types of memory devices; and

send control information to a second memory type of the different types of memory devices.

16. A memory controller, comprising:

clock circuitry configured to provide clock signals having different clock rates for different types of memory devices; and

an interface circuit configured to time division multiplex data destined for the different types of memory devices on a shared signal bus such that the data is output at the different clock rates for the different types of memory devices;

the clock signals comprising a first clock signal, a second clock signal, and at least one other clock signal;

the first clock signal to operate at a first native clock rate associated with write operations for a first one of the memory device types;

the second clock signal to operate at a second native clock rate associated with read operations for the first one of the memory device types; and

the at least one other clock signal to operate at a third native clock rate associated with read and write operations for a second one of the memory device types.

17. A memory control apparatus, comprising:

means for providing clock signals having different clock rates for different types of memory devices; and

means for time division multiplexing data destined for the different types of memory devices on a shared signal bus such that the data is output at the different clock rates for the different types of memory devices;

means for providing first write data at a first one of the clock rates for write operations directed to a first type of memory device of the different types of memory devices, wherein the first type of memory device is configured to transmit and receive over the shared signal bus at the first clock rate, and

means for providing second write data at the first clock rate for write operations directed to a second type of memory device of the different types of memory devices, wherein the second type of memory device is configured to transmit and receive over the shared signal bus at a second one of the clock rates that is slower than the first clock rate, and a portion of the second write data comprises dummy data.