Semiconductor device
A semiconductor device includes a stripe-shaped gate trench formed in one major surface of n-type drift layer, a gate trench including gate polysilicon formed therein, and a gate polysilicon connected to a gate electrode. A p-type base layer is formed selectively in mesa region between adjacent gate trenches and a p-type base layer including an n-type emitter layer and connected to emitter electrode. One or more dummy trenches are formed between p-type base layers adjoining to each other in the extending direction of gate trenches. An electrically conductive dummy polysilicon is formed on an inner side wall of dummy trench with a gate oxide film interposed between the dummy polysilicon and dummy trench. The dummy polysilicon is spaced apart from the gate polysilicon and may be connected to the emitter electrode.
1. A semiconductor device comprising:
a first semiconductor layer of a first conductivity type;
a second semiconductor layer of a second conductivity type formed above the first semiconductor layer;
a first trench formed in a surface of the second semiconductor layer, the first trench being shaped with a stripe;
a gate electrode formed in the first trench with an insulator film ( 10 ) interposed between the gate electrode and the first trench;
a third semiconductor layer of the first conductivity type formed selectively between the first trenches in an extending direction of the first trenches;
a fourth semiconductor layer of the second conductivity type formed selectively in a surface of the third semiconductor layer;
an emitter electrode in contact with the third semiconductor layer and the fourth semiconductor layer;
a collector electrode in contact with the first semiconductor layer;
a second trench formed between the first trenches adjacent to each other, the second trench being formed in parallel to the first trenches adjacent to each other, and the second trench being formed between two of the third semiconductor layers; and
a mesa region exposed in a surface of the second semiconductor layer and arranged along the longitudinal direction of the trenches,
the mesa region being sandwiched by the second semiconductor layer and the first and second trenches, and contacting the emitter electrode via the third semiconductor layer, such that the third semiconductor layer and the second semiconductor layer are exposed alternately in the surface.
2. The semiconductor device according to claim 1 , the semiconductor device further comprising a first electrical conductor buried in the second trench with an insulator film interposed between the first electrical conductor and the second trench, the first electrical conductor being spaced apart from the gate electrode.
3. The semiconductor device according to claim 2 , wherein the first electrical conductor is connected to the emitter electrode.
4. The semiconductor device according to claim 3 , wherein the first electrical conductor is connected to the emitter electrode in a distal end portion of the second trench in an extending direction of the second trench.
5. The semiconductor device according to claim 2 , wherein two or more of the second trenches are formed between the first trenches adjacent to each other.
6. The semiconductor device according to claim 5 , wherein the first electrical conductors formed in two or more of the second trenches are connected electrically to each other for setting the first electrical conductors at a same potential.
7. The semiconductor device according to claim 6 , wherein the second trenches adjacent to each other are connected to each other in distal end portions of the second trenches in an extending direction of the second trenches, and
the first electrical conductors formed in the second trenches are connected to each other in the distal end portions.
8. The semiconductor device according to claim 6 , the semiconductor device further comprising a second electrical conductor on upper surfaces of the second trenches adjacent to each other, the second electrical conductor being in contact with the first electrical conductors for connecting the first electrical conductors in the second trenches to each other, and
the second electrical conductor being connected to the emitter electrode in a part of the second electrical conductor.
9. The semiconductor device according to claim 2 , wherein the first electrical conductor is separated from the emitter electrode, the collector electrode, and the gate electrode for setting the first electrical conductor at a floating potential.
10. The semiconductor device according to any of claim 1 , wherein the first trench and the second trench are in contact with each other on a side wall of the first trench along the extending direction of the first trench or on a side wall of the second trench along an extending direction of the second trench.
11. The semiconductor device according to claim 1 , wherein a distance between the first trench and the second trench is shorter than a width of a built-in depletion layer that expands, in a thermal equilibrium state, into the second semiconductor layer from a pn-junction between the second semiconductor layer and the third semiconductor layer.
12. The semiconductor device according to claim 2 , wherein a distance between the first trench and the second trench is shorter than a width of a built-in depletion layer that expands, in a thermal equilibrium state, into the second semiconductor layer from a pn-junction between the second semiconductor layer and the third semiconductor layer.
13. The semiconductor device according to claim 3 , wherein a distance between the first trench and the second trench is shorter than a width of a built-in depletion layer that expands, in a thermal equilibrium state, into the second semiconductor layer from a pn-junction between the second semiconductor layer and the third semiconductor layer.
14. The semiconductor device according to claim 4 , wherein a distance between the first trench and the second trench is shorter than a width of a built-in depletion layer that expands, in a thermal equilibrium state, into the second semiconductor layer from a pn-junction between the second semiconductor layer and the third semiconductor layer.
15. The semiconductor device according to claim 5 , wherein a distance between the first trench and the second trench is shorter than a width of a built-in depletion layer that expands, in a thermal equilibrium state, into the second semiconductor layer from a pn-junction between the second semiconductor layer and the third semiconductor layer.
16. The semiconductor device according to claim 6 , wherein a distance between the first trench and the second trench is shorter than a width of a built-in depletion layer that expands, in a thermal equilibrium state, into the second semiconductor layer from a pn-junction between the second semiconductor layer and the third semiconductor layer.
17. The semiconductor device according to claim 7 , wherein a distance between the first trench and the second trench is shorter than a width of a built-in depletion layer that expands, in a thermal equilibrium state, into the second semiconductor layer from a pn-junction between the second semiconductor layer and the third semiconductor layer.
18. The semiconductor device according to claim 8 , wherein a distance between the first trench and the second trench is shorter than a width of a built-in depletion layer that expands, in a thermal equilibrium state, into the second semiconductor layer from a pn-junction between the second semiconductor layer and the third semiconductor layer.
19. The semiconductor device according to claim 9 , wherein a distance between the first trench and the second trench is shorter than a width of a built-in depletion layer that expands, in a thermal equilibrium state, into the second semiconductor layer from a pn-junction between the second semiconductor layer and the third semiconductor layer.
20. The semiconductor device according to claim 10 , wherein a distance between the first trench and the second trench is shorter than a width of a built-in depletion layer that expands, in a thermal equilibrium state, into the second semiconductor layer from a pn-junction between the second semiconductor layer and the third semiconductor layer.