IP Library Granted Patent US 8,372,709
Granted Patent B2
US 8,372,709 · App. 13/584,926 · Granted Feb 12, 2013

Semiconductor device and method of manufacturing the same

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,372,709
App. No.
13/584,926
Granted
Feb 12, 2013
Kind
B2
Abstract

A method of forming a semiconductor device includes forming an interfacial layer on a semiconductor substrate, forming a high-k dielectric on the interfacial layer, forming a barrier metal on the high-k dielectric, forming a poly-silicon layer on the barrier metal, patterning the interfacial layer, the high-k dielectric, the barrier metal and the poly-silicon to form a gate stack forming spacers, extension regions, sidewalls and source/drain regions, forming an interlayer dielectric on the gate stack, etching off a portion of the interlayer dielectric to expose the poly-silicon layer, forming an impurity metal layer, which includes an impurity metal having a barrier effect to the diffusive material, and a metal layer including a diffusive material, on the poly-silicon layer and converting the poly-Si layer into a silicide containing the impurity metal. The barrier metal includes a titanium nitride (TiN) or a tantalum nitride (TaN).

Claims (16)

1. A method of forming a semiconductor device, comprising:

forming an interfacial layer on a semiconductor substrate;

forming a high-k dielectric on the interfacial layer;

forming a barrier metal on the high-k dielectric;

forming a poly-silicon layer on the barrier metal,

patterning the interfacial layer, the high-k dielectric, the barrier metal and the poly-silicon to form a gate stack forming spacers, extension regions, sidewalls and source/drain regions,

forming an interlayer dielectric on the gate stack;

etching off a portion of the interlayer dielectric to expose the poly-silicon layer;

forming an impurity metal layer, which includes an impurity metal having a barrier effect to the diffusive material, and a metal layer including a diffusive material, on the poly-silicon layer; and

converting the poly-silicon layer into a silicide containing the impurity metal, wherein the barrier metal comprises a titanium nitride (TiN) or a tantalum nitride (TaN).

2. The method of forming a semiconductor device, as claimed in claim 1 , wherein the impurity material is locally located so that a peak of the concentration of the impurity metal is located at a boundary between the barrier metal and the silicide gate.

3. The method of forming a semiconductor device, as claimed in claim 1 , wherein the high-k dielectric includes a Hf-based high-k dielectric or Zr-based high-k dielectric.

4. The method of forming a semiconductor device, as claimed in claim 1 , wherein barrier metal has a thickness of 3 nm or less.

5. The method of forming a semiconductor device, as claimed in claim 4 , wherein the thickness of the barrier metal comprises a thickness of 1.5 nm or less.

6. The method of forming a semiconductor device, as claimed in claim 1 , wherein the diffusive material includes Ni.

7. The method of forming a semiconductor device, as claimed in claim 1 , wherein the impurity metal comprises Pt or Al.

Assignments (4)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED AT REEL: 053654 FRAME: 0254. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jun 10, 2021
From: STARBOARD VALUE INTERMEDIATE FUND LP
To: ACACIA RESEARCH GROUP LLC
Reel/Frame 057454/0045 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR NAME PREVIOUSLY RECORDED ON REEL 052853 FRAME 0153. ASSIGNOR(S) HEREBY CONFIRMS THE PATENT SECURITY AGREEMENT. Recorded Mar 2, 2021
From: ACACIA RESEARCH GROUP LLC
To: STARBOARD VALUE INTERMEDIATE FUND LP, AS COLLATERAL AGENT
Reel/Frame 056775/0066 →
RELEASE OF SECURITY INTEREST IN PATENTS Recorded Jul 8, 2020
From: STARBOARD VALUE INTERMEDIATE FUND LP
To: ACACIA RESEARCH GROUP LLC; AMERICAN VEHICULAR SCIENCES LLC; BONUTTI SKELETAL INNOVATIONS LLC; CELLULAR COMMUNICATIONS EQUIPMENT LLC; INNOVATIVE DISPLAY TECHNOLOGIES LLC; LIFEPORT SCIENCES LLC; LIMESTONE MEMORY SYSTEMS LLC; MOBILE ENHANCEMENT SOLUTIONS LLC; MONARCH NETWORKING SOLUTIONS LLC; NEXUS DISPLAY TECHNOLOGIES LLC; PARTHENON UNIFIED MEMORY ARCHITECTURE LLC; R2 SOLUTIONS LLC; SAINT LAWRENCE COMMUNICATIONS LLC; STINGRAY IP SOLUTIONS LLC; SUPER INTERCONNECT TECHNOLOGIES LLC; TELECONFERENCE SYSTEMS LLC; UNIFICATION TECHNOLOGIES LLC
Reel/Frame 053654/0254 →
PATENT SECURITY AGREEMENT Recorded Jun 5, 2020
From: ACACIA RESEARCH GROUP LLC; AMERICAN VEHICULAR SCIENCES LLC; BONUTTI SKELETAL INNOVATIONS LLC; CELLULAR COMMUNICATIONS EQUIPMENT LLC; INNOVATIVE DISPLAY TECHNOLOGIES LLC; LIFEPORT SCIENCES LLC; LIMESTONE MEMORY SYSTEMS LLC; MERTON ACQUISITION HOLDCO LLC; MOBILE ENHANCEMENT SOLUTIONS LLC; MONARCH NETWORKING SOLUTIONS LLC; NEXUS DISPLAY TECHNOLOGIES LLC; PARTHENON UNIFIED MEMORY ARCHITECTURE LLC; R2 SOLUTIONS LLC; SAINT LAWRENCE COMMUNICATIONS LLC; STINGRAY IP SOLUTIONS LLC; SUPER INTERCONNECT TECHNOLOGIES LLC; TELECONFERENCE SYSTEMS LLC; UNIFICATION TECHNOLOGIES LLC
To: STARBOARD VALUE INTERMEDIATE FUND LP, AS COLLATERAL AGENT
Reel/Frame 052853/0153 →