Printed non-volatile memory

1. A non-volatile memory cell, comprising:

a) first and second semiconductor islands at a same horizontal level on a substrate and spaced a predetermined distance apart, the first semiconductor island comprising a control gate of said non-volatile memory cell and the second semiconductor island comprising source and drain terminals of said non-volatile memory cell;

b) a gate dielectric layer on at least part of said first semiconductor island;

c) a tunneling dielectric layer on at least part of said second semiconductor island;

d) a floating gate on at least part of said gate dielectric layer and said tunneling dielectric layer; and

e) a metal layer in electrical contact with said control gate and said source and drain terminals.

2. The non-volatile memory cell of claim 1 , wherein each of said first and second semiconductor islands has an area defined by a width and a length, and the width and/or length of said first semiconductor island is substantially equal to at least one of said width and/or length of said second semiconductor island.

3. The non-volatile memory cell of claim 1 , wherein said gate dielectric layer and said tunneling dielectric layer are conformal to said semiconductor islands.

4. The non-volatile memory cell of claim 1 , wherein the first and second semiconductor islands have a rounded and/or dome-shaped profile.

5. The non-volatile memory cell of claim 4 , wherein said floating gate has a rounded and/or dome-shaped cross-sectional profile.

6. The non-volatile memory cell of claim 1 , wherein said floating gate is continuous.

7. An integrated circuit, comprising:

a) non-volatile memory cell of claim 1 ; and

b) a MOS transistor comprising:

i) a third semiconductor island, at the same horizontal level as the first and second semiconductor islands;

ii) a MOS gate dielectric on at least part of said third semiconductor island; and

iii) a gate electrode on at least part of said MOS gate dielectric.

8. A method of programming or erasing the non-volatile memory cell of claim 1 , comprising:

a) holding the source and drain terminals of the second semiconductor island at a ground potential; and

b) applying a first positive voltage or a first negative voltage to the first semiconductor island for a length of time sufficient to program or erase the non-volatile memory cell.

9. The method of claim 8 , wherein the first positive voltage is applied to the control gate, the first positive voltage being at least 12V.

10. The method of claim 9 , wherein the first positive voltage is from about 20V to 25V.

11. A method of reading the non-volatile memory cell of claim 1 , comprising:

a) holding the source and drain terminals of the second semiconductor island at a ground potential;

b) applying a first positive voltage or a first negative voltage to the first semiconductor island for a length of time sufficient to program or erase the non-volatile memory cell;

c) applying a second positive voltage to the control gate;

d) applying a third positive voltage to the drain; and

e) holding the source at a ground potential.

12. The method of claim 11 , wherein the second and third positive voltages are from about 1.5V to 9V.

13. The method of claim 12 , wherein the second and third positive voltages are from about 3V to 5V.

14. A method for making the non-volatile memory cell of claim 1 , comprising:

a) forming, from a semiconductor ink, a plurality of semiconductor islands on a substantially horizontal uppermost surface of the substrate, wherein a first semiconductor island is a control gate and a second semiconductor island is a transistor island;

b) forming the gate dielectric layer on at least part of said control gate and the tunneling dielectric layer on at least part of said transistor island;

c) forming a continuous floating gate on at least part of said gate dielectric layer and said tunneling dielectric layer;

d) forming a dielectric film on said control gate, said transistor island, and said floating gate; and

e) forming the metal layer in electrical contact with said control gate and said transistor island.

15. The method of claim 14 , wherein said semiconductor ink comprises a silane in an amount of from 1 to 50 wt. % of said ink and a solvent in which said silane is soluble.

16. The method of claim 15 , wherein forming the plurality of semiconductor islands comprises printing the semiconductor ink onto the substantially horizontal uppermost surface of the substrate.

17. The method of claim 14 , wherein forming the dielectric film comprises printing the dielectric film on or over said control gate and said transistor island, said dielectric film containing a diffusible dopant.

18. The method of claim 14 , wherein:

forming the gate dielectric layer and/or the tunneling dielectric layer comprises plasma or low-pressure chemical vapor deposition of the gate dielectric layer, thermal oxidation of a surface of the control gate and/or the transistor island, or liquid phase or chemical bath deposition of a gate dielectric precursor; and

the tunneling dielectric layer and the gate dielectric layer are formed simultaneously.

19. The method of claim 14 , further comprising forming a gate in a MOS transistor simultaneously with forming the floating gate.

20. The method of claim 19 , further comprising:

forming a MOS transistor channel simultaneously with forming the plurality of semiconductor islands; and

forming a MOS transistor gate oxide simultaneously with forming the gate dielectric layer and/or tunneling dielectric layer.