Common mode input control for switch capacitor amplifier in pipeline analog-to-digital converter
View Patent ↗A common mode bias circuit may include a weak common mode bias generator and a common mode bias capacitance. During a first state of the common mode bias circuit, the weak common mode bias generator may be coupled to the common mode bias capacitance and may impart to them a predefined common mode signal level. During a second state of the common mode bias circuit, the common mode bias capacitance may be coupled to differential inputs of an amplifier in a manner that establishes an input common mode level for the amplifier.
1. A common mode bias circuit comprising:
a common mode bias generator; and
a common mode bias capacitance that has a first and a second terminal;
wherein the common mode bias circuit is configured such that:
during a first state of the common mode bias circuit:
the common mode bias generator is coupled to the first terminal of the common mode capacitance and imparts to it a predefined common mode signal level; and
the second terminal of the common mode bias capacitance is coupled to a DC bias voltage;
during a second state of the common mode bias circuit:
the first terminal of the common mode bias capacitance is coupled to differential inputs of an amplifier in a manner that establishes an input common mode level for the amplifier; and
the second terminal of the common mode bias capacitance remains coupled to the DC bias voltage; and
the DC bias voltage remains substantially the same during the first and second states.
2. The common mode bias circuit of claim 1 wherein the common mode bias circuit is part of a pipeline analog-to-digital converter.
3. The common mode bias circuit of claim 1 wherein the common mode bias generator is a weak common mode bias generator.
4. The common mode bias circuit of claim 1 wherein:
the common mode bias capacitance is a capacitor having a first and a second terminal;
the first terminal of the common mode capacitance is the first terminal of the capacitor; and
the second terminal of the common mode capacitance is the second terminal of the capacitor.
5. The common mode bias circuit of claim 1 wherein the common mode bias circuit is part of a larger circuit that performs digital-to-analog conversion.
6. The common mode bias circuit of claim 5 wherein the common mode bias circuit has both a sample state and a hold state.
7. The common mode bias circuit of claim 6 wherein the first state is the sample state and the second state is the hold state.
8. The common mode bias circuit of claim 1 wherein:
the common mode bias capacitance is a first common mode bias capacitance and further comprising a second common mode bias capacitance that has a first and a second terminal and that is different than the first common mode bias capacitance; and
the common mode bias circuit is configured such that:
during the first state of the common mode bias circuit:
the common mode bias generator is coupled to the first terminal of the second common mode capacitance and imparts to it a predefined common mode signal level; and
the second terminal of the second common mode bias capacitance is coupled to a DC bias voltage; and
during the second state of the common mode bias circuit:
the first terminal of the second common mode bias capacitance is coupled to the differential inputs of the amplifier in a manner that helps establish an input common mode level for the amplifier; and
the second terminal of the second common mode bias capacitance remains coupled to the DC bias voltage.