IP Library Granted Patent US 9,000,535
Granted Patent B2
US 9,000,535 · App. 13/587,999 · Granted Apr 7, 2015

Semiconductor device and semiconductor device manufacturing method

Inventor: Masatoshi Fukuda (Akiruno, JP)
Assignee: Fujitsu Semiconductor Limited
H01L27/088H01L21/823475H01L27/0207H01L21/76895H01L21/76807H01L21/76816H01L27/1104H01L27/1116H01L29/7833
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Quick Facts
Patent No.
US 9,000,535
App. No.
13/587,999
Granted
Apr 7, 2015
Kind
B2
Abstract

A semiconductor device includes: a semiconductor substrate; a first transistor which is formed on the semiconductor substrate and includes a source/drain region and a gate electrode; an insulating film which covers the source/drain region and the gate electrode of the first transistor; and a first contact plug which is formed in the insulating film and is connected to the source/drain region or the gate electrode of the first transistor, wherein the first contact plug includes a first column section which extends in a thickness direction of the insulating film and is in contact with the source/drain region or the gate electrode of the first transistor, and a first flange section which juts out from an upper portion of the first column section in a direction parallel to a surface of the insulating film, and an upper surface of the first flange section is planarized.

Claims (37)

1. A semiconductor device comprising:

a semiconductor substrate;

a first transistor, that includes a first source/drain region and a first gate electrode, formed on the semiconductor substrate;

a second transistor, that includes a second source/drain region and a second gate electrode, formed on the semiconductor substrate;

an insulating film that covers the first and second source/drain regions and the first and second gate electrodes; and

a first contact plug formed in the insulating film and connected to the first source/drain region and the second gate electrode,

wherein:

the first contact plug includes a first column section, a second column section and a first flange section,

the first column section extends from the first flange section to the first source/drain region and is in contact with the first source/drain region,

the second column section extends from the first flange section to the second gate electrode and is in contact with the second gate electrode,

the first flange section juts out from an upper portion of the first column section and an upper portion of the second column section in a plan view, and an upper surface of the first flange section is planarized,

the first column section, the second column section and the flange section include a same material, and

the first flange section is connected to the first column section and the second column section.

2. The semiconductor device according to claim 1 , wherein the first transistor and the second transistor are load transistors in an SRAM.

3. The semiconductor device according to claim 1 , wherein

the first column section and the second column section are disposed side by side in a direction intersecting an extending direction of the gate electrode of the second transistor, and

the first flange section juts out in a direction intersecting the extending direction of the gate electrode of the second transistor.

4. The semiconductor device according to claim 1 ,

further comprising

a third transistor, that includes a third source/drain region and a third gate electrode, formed on the semiconductor substrate; and

a second contact plug formed in the insulating film and connected to the third source/drain region or the third gate electrode,

wherein:

the insulating film covers the third source/drain region and the third gate electrode,

the second contact plug includes a third column section and a second flange section,

the third column section extends from the second flange section to the third source/drain region or third gate electrode and is in contact with the third source/drain region or the third gate electrode, and

the second flange section juts out from an upper portion of the third column section in a plan view and has a planarized upper surface; and

a cross section of the third column section has a same shape of a cross section of the first column shape or a cross section of the second column shape.

5. The semiconductor device according to claim 1 , wherein the first flange section juts out either in a direction intersecting the extending direction of the first gate electrode, or in a direction parallel to the extending direction of the first gate electrode.

6. The semiconductor device according to claim 5 , wherein with respect to a direction intersecting the direction in which the first flange section juts out, a dimension of the first flange section and a dimension of the first column section are equal to each other.

7. The semiconductor device according to claim 1 , wherein:

the insulating film includes

a first insulating film and

a second insulating film, that includes a material different from a material of the first insulating film, formed on the first insulating film;

the first column section is disposed in the first insulating film;

the first flange section is disposed in the second insulating film; and

an upper surface of the second insulating film and an upper surface of the first flange section are flush with each other.

8. The semiconductor device according to claim 1 , further comprising a wiring layer formed on the first flange section.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2025
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 073964/0516 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 27, 2024
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 069454/0333 →
MERGER Recorded May 24, 2023
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU LIMITED
Reel/Frame 064221/0545 →
CHANGE OF NAME AND CHANGE OF ADDRESS Recorded Jul 16, 2020
From: AIZU FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053481/0962 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2020
From: FUJITSU SEMICONDUCTOR LIMITED
To: AIZU FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053209/0468 →
CHANGE OF ADDRESS Recorded Dec 23, 2016
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 041188/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 29, 2012
From: FUKUDA, MASATOSHI
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 028867/0143 →
Priority Claims (1)
JP 2011-220009 · Oct 4, 2011 · national
Continuity (1)
Related Publication 20130082331A1 · Apr 4, 2013