IP Library Granted Patent US 8,478,336
Granted Patent B2
US 8,478,336 · App. 13/589,267 · Granted Jul 2, 2013

Baseband / RFIC interface for high throughput MIMO communications

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,478,336
App. No.
13/589,267
Granted
Jul 2, 2013
Kind
B2
Abstract

Analog signal paths are utilized between a baseband processor and a radio front end to support high throughput communications for a multiple in multiple out radio transceiver that support communications over two or more antennas. Specifically, analog differential I and Q path communication signals are exchanged between a radio front end core and a baseband processor to maximize throughput capacity for high data rate signals. Along the same lines, the impedances of traces and the interface are matched to reduce I/Q imbalance.

Claims (36)

1. A multiple-input-multiple-output (MIMO) radio transceiver, comprising:

a plurality of front end cores, each servicing respective receive in-phase and quadrature phase differential signals and transmit in-phase and quadrature phase differential signals of a plurality of MIMO signals and including a plurality of Received Signal Strength Indicator (RSSI) circuits; and

a MIMO signal interface coupling the plurality of front end cores to at least one baseband processor and configured to receive an RSSI select signal to select at least one output of the plurality of RSSI circuits.

2. The MIMO radio transceiver of claim 1 , further comprising a plurality of Analog to Digital Converters (ADCs), each servicing a respective differential signal path.

3. The MIMO radio transceiver of claim 1 , further comprising a plurality of Digital to Analog Converters (DACs), each servicing a respective differential signal path.

4. The MIMO radio transceiver of claim 1 :

wherein at least one front end core of the plurality of front end cores comprises two Rx/Tx processing blocks; and

further comprising sixteen differential analog signal paths coupling the at least one front end core to the at least one baseband processor.

5. The MIMO radio transceiver of claim 1 , wherein:

at least one front end core further comprises:

at least one low pass filter having quality tunable based upon at least one filter input signal; and

at least one high pass filter having a bandwidth selectable based upon the at least one filter input signal; and

the MIMO signal interface further receiving the at least one filter input signal.

6. The MIMO radio transceiver of claim 1 , further comprising a plurality of antennas operable to concurrently service at least two active communication links.

7. The MIMO radio transceiver of claim 1 , wherein each in-phase and quadrature phase transmit path is impedance matched to reduce I/Q imbalance.

8. The MIMO radio transceiver of claim 1 , wherein the MIMO signal interface is operable to service both ingoing and outgoing differential signals during overlapping signal periods.

9. A method for operating a multiple-input-multiple-output (MIMO) transceiver comprising:

at each of a plurality of front end cores of the MIMO transceiver, servicing respective receive in-phase and quadrature phase differential signals and transmit in-phase and quadrature phase differential signals of a plurality of MIMO signals;

by a MIMO signal interface, coupling the plurality of front end cores to at least one baseband processor and receiving a Received Signal Strength Indicator (RSSI) select signal; and

selecting, based upon the RSSI select signal, one of a plurality of RSSI circuits of the plurality of front end cores of the MIMO transceiver for output.

10. The method of claim 9 , further comprising respective differential signal path by a plurality of Analog to Digital Converters (ADCs).

11. The method of claim 9 , further comprising servicing a respective differential signal path by a plurality of Digital to Analog Converters (DACs).

12. The method of claim 9 , further comprising coupling the at least one front end core to the at least one baseband processor by sixteen differential analog signal paths.

13. The method of claim 9 , further comprising:

receiving at least one filter input signal;

tuning at least one low pass filter based upon the at least one filter input signal; and

tuning at least one bandwidth selectable high pass filter based upon the at least one filter input signal.

14. The method of claim 9 , further comprising concurrently servicing at least two active communication links via a plurality of antennas.

15. The method of claim 9 , further comprising impedance matching each in-phase and quadrature phase transmit path to reduce I/Q imbalance.

16. The method of claim 9 , further comprising servicing both ingoing and outgoing differential signals during overlapping signal periods.

17. A multiple-input-multiple-output (MIMO) radio transceiver, comprising:

a plurality of front end cores, each comprising at least two Rx/Tx processing blocks and servicing respective receive in-phase and quadrature phase differential signals and transmit in-phase and quadrature phase differential signals of a plurality of MIMO signals; and

a MIMO signal interface coupling the plurality of front end cores to at least one baseband processor, the MIMO signal interface comprising, for each front end core, at least sixteen differential analog signal paths coupling the front end core to the at least one baseband processor.

18. The MIMO radio transceiver of claim 17 , further comprising a plurality of antennas operable to concurrently service at least two active communication links.

19. The MIMO radio transceiver of claim 17 , wherein each in-phase and quadrature phase transmit path is impedance matched to reduce I/Q imbalance.

20. The MIMO radio transceiver of claim 17 , further comprising a plurality of Analog to Digital Converters (ADCs), each servicing a respective differential signal path.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER TO 09/05/2018 PREVIOUSLY RECORDED AT REEL: 047230 FRAME: 0133. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047630/0456 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047230/0133 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 20, 2012
From: TRACHEWSKY, JASON A.; BEHZAD, ARYA REZA
To: BROADCOM CORPORATION
Reel/Frame 028811/0350 →