IP Library Granted Patent US 8,791,753
Granted Patent B2
US 8,791,753 · App. 13/591,136 · Granted Jul 29, 2014

Slew rate and bandwidth enhancement in reset

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Quick Facts
Patent No.
US 8,791,753
App. No.
13/591,136
Granted
Jul 29, 2014
Kind
B2
Abstract

Embodiments of a capacitance sensing system including an integrating amplifier and methods for operating the same to provide a higher slew rate and bandwidth are described. In one embodiment, the integrating amplifier comprises an input stage including an inverting input coupled to an electrode of a capacitor to sense a capacitance and a non-inverting input coupled to a reference potential, and an output stage including a compensating capacitor coupled to an output. The compensating capacitor comprises two smaller capacitors coupled in parallel and a switching element configured to open when the integrating amplifier is operated in a RESET mode decoupling one of the two smaller capacitors from the output to decrease capacitance of the compensating capacitor.

Claims (28)

1. An integrating amplifier comprising:

an input stage including an inverting input coupled to an electrode of a sense capacitor to sense a capacitance thereof and a non-inverting input coupled to a reference potential; and

an output stage including a compensating capacitor coupled to an output, the compensating capacitor comprising two smaller capacitors coupled in parallel and a switching element configured to open when the integrating amplifier is operated in a RESET mode decoupling one of the two smaller capacitors from the output to decrease capacitance of the compensating capacitor when the integrating amplifier is operated in RESET mode, and to close when the integrating amplifier is operated in an INTEGRATION mode.

2. The integrating amplifier of claim 1 , further comprising a plurality of diode connected devices coupled in parallel when the integrating amplifier is operated in RESET mode to provide greater stability.

3. The integrating amplifier of claim 2 , wherein the plurality of diode connected devices comprises parallel diode connected devices, and wherein one of the parallel diode connected devices is switched into an output stage current path when the integrating amplifier is operated in RESET mode to provide greater stability.

4. The integrating amplifier of claim 1 , further comprising an integration capacitor and switch coupled in parallel between the inverting input of the integrating amplifier and the output, wherein the switch is opened when the integrating amplifier is operated in an integration mode to accumulate charge from the sense capacitor, and closed during RESET mode to reset the integration capacitor.

5. The integrating amplifier of claim 1 , wherein the two smaller capacitors of the compensating capacitor comprise capacitances selected so that the capacitance of the compensating capacitor is decreased by at least 10% when the integrating amplifier is operated in RESET mode.

6. The integrating amplifier of claim 1 , wherein the two smaller capacitors of the compensating capacitor comprise capacitances selected so that the capacitance of the compensating capacitor is decreased by about 50% when the integrating amplifier is operated in RESET mode.

7. A capacitance sensing system comprising:

an integrating amplifier including an input stage including an inverting input coupled to an electrode of a sense capacitor to be sensed and a non-inverting input coupled to a reference voltage, and an output stage including a compensating capacitor coupled to an output;

an integration capacitor coupled between the inverting input of the integrating amplifier and the output to accumulate charge from the sense capacitor when the integrating amplifier is operated in an integration mode; and

a switch coupled in parallel with the integration capacitor between the inverting input of the integrating amplifier and the output, the switch configured to be open in integration mode and closed when the integrating amplifier is operated in RESET mode to reset the capacitor,

wherein the integrating amplifier further comprises a device plurality of diode connected devices coupled in parallel to increase an output stage current when the integrating amplifier is operated in RESET mode.

8. The capacitance sensing system of claim 7 , wherein the plurality of diode connected devices comprises parallel diode connected devices, and wherein one of the parallel diode connected devices is switched into an output stage current path when the integrating amplifier is operated in RESET mode to provide greater stability.

9. The capacitance sensing system of claim 7 , wherein the compensating capacitor comprises two smaller capacitors coupled in parallel and a switching element configured to open when the integrating amplifier is operated in a RESET mode decoupling one of the two smaller capacitors from the output to decrease capacitance of the compensating capacitor when the integrating amplifier is operated in RESET mode.

10. The capacitance sensing system of claim 9 , wherein the two smaller capacitors of the compensating capacitor comprise capacitances selected so that the capacitance of the compensating capacitor is decreased by at least 10% when the integrating amplifier is operated in RESET mode.

11. The capacitance sensing system 9 , wherein the two smaller capacitors of the compensating capacitor comprise capacitances selected so that the capacitance of the compensating capacitor is decreased by about 50% when the integrating amplifier is operated in RESET mode.

12. A method for sensing capacitance of a capacitor, comprising:

accumulating a charge received on a receive electrode of a sense capacitor using a capacitance sensing system including an integrating amplifier comprising an input stage including an inverting input coupled to the receive electrode, and an output stage including a compensating capacitor coupled to an output; and

resetting the capacitance sensing system after a period of time, wherein resetting the capacitance sensing system comprises increasing the slew rate and gain-bandwidth (GBW) of the integrating amplifier.

13. The method of claim 12 , wherein increasing the slew rate and GBW of the integrating amplifier comprises decreasing capacitance of the compensating capacitor while the integrating amplifier is operated in a RESET mode.

14. The method of claim 13 , wherein the compensating capacitor comprises two smaller capacitors coupled in parallel and a switching element configured to open when the integrating amplifier is operated in RESET mode, and wherein decreasing capacitance of the compensating capacitor comprises opening the switching element to decouple one of the two smaller capacitors from the output to decrease capacitance of the compensating capacitor.

15. The method of claim 13 , wherein decreasing capacitance of the compensating capacitor while the integrating amplifier is operated in a RESET mode comprises decreasing capacitance of the compensating capacitor by about 50%.

16. The method of claim 12 , wherein the capacitance sensing system further comprises an integration capacitor and switch coupled in parallel between the inverting input of the integrating amplifier and the output, and wherein resetting the capacitance sensing system further comprises closing the switch to reset the integration capacitor.

17. The method of claim 12 , wherein resetting the capacitance sensing system further comprises increasing an output stage current of the integrating amplifier to provide greater stability.

18. The method of claim 17 , wherein the capacitance sensing system further comprises a first diode connected device, and wherein increasing an output stage current of the integrating amplifier comprises enabling a second diode connected device in parallel with the first first diode connected device when the integrating amplifier is operated in RESET mode.

19. The method of claim 12 , wherein resetting the capacitance sensing system does not comprise decoupling the receive electrode from the capacitance sensing system.

20. The integrating amplifier of claim 1 , wherein the switching element is configured to open only when the integrating amplifier is operated in a RESET mode.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 31, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION
To: PARADE TECHNOLOGIES, LTD.
Reel/Frame 036508/0284 →
PARTIAL RELEASE OF SECURITY INTEREST IN PATENTS AND TRADEMARKS Recorded Aug 4, 2015
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT FOR THE SECURED PARTIES
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036264/0114 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
PATENT SECURITY AGREEMENT Recorded Nov 14, 2013
From: CYPRESS SEMICONDUCTOR CORPORATION
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 031636/0105 →
CORRECTIVE ASSIGNMENT TO CORRECT THE DOCKET NUMBER IN BOX 5 OF FORM PTO-1595 FROM CD12040 TO CD12007 OF THE ASSIGNMENT PREVIOUSLY RECORDED ON REEL 028825 FRAME 0321. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT OF ASSIGNORS INTEREST. Recorded Oct 4, 2012
From: MURUGESAN, SARAVANAN V.; WALSH, PAUL; BALDWIN, GERARD; HOSSEINI, KAVEH
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 029087/0235 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 21, 2012
From: MURUGESAN, SARAVANAN; WALSH, PAUL; BALDWIN, GERARD; HOSSEINI, KAVEH
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 028825/0321 →