Semiconductor memory device, information processing system including the same, and controller

1. A system comprising:

a controller that includes:

first and second selection-signal terminals supplying first and second selection-signals, respectively;

a plurality of first data terminals; and

a plurality of second data terminals; and

a memory chip that includes:

a semiconductor substrate;

third and fourth selection-signal terminals provided on the semiconductor substrate and being electrically coupled to the first and second selection-signal terminals of the controller, respectively;

a plurality of third data terminals provided on the semiconductor substrate and being electrically coupled to the first data terminals of the controller, respectively; and

a plurality of fourth data terminals provided on the semiconductor substrate and being electrically coupled to the second data terminals of the controller, respectively;

the first and third data terminals communicating first data in response to the first selection-signal, the second and fourth data terminals communicating second data in response to the second selection-signal.

2. The system as claimed in claim 1 , wherein the memory chip further includes first and second mode registers each provided on the semiconductor substrate, the first mode register storing first information in response to the first selection-signal, the second mode register storing second information in response to the second selection-signal.

3. The system as claimed in claim 2 , wherein the memory chip further includes first and second circuits each provided on the semiconductor substrate, the first and second circuits being substantially same in configuration as each other, the first and second circuits performing an operation in response to the information of the first and second mode registers, respectively.

4. The system as claimed in claim 3 , wherein the first and second circuits memorize the first and second data, respectively.

5. The system as claimed in claim 4 , wherein the first and second circuits respectively output the first and second data to the third and fourth data terminals substantially simultaneously with each other.

6. The system as claimed in claim 3 , wherein the first and second circuits performing an operation in response to the information of the first and second mode registers, respectively.

7. The system as claimed in claim 6 , wherein the operation that includes at least one of a read operation of a corresponding one of the first and second circuits and a write operation of a corresponding one of the first and second circuits.

8. The system as claimed in claim 7 , wherein the read operation includes a refresh operation.

9. A system comprising:

a controller that includes first and second selection-signal terminals supplying first and second selection-signals, respectively; and

a memory chip that includes:

a semiconductor substrate;

third and fourth selection-signal terminals provided on the semiconductor substrate and being electrically coupled to the first and second selection-signal terminals of the controller to receive the first and second selection-signals, respectively;

first and second mode registers each provided on the semiconductor substrate, the first mode register storing first information in response to the first selection-signal, the second mode register storing second information in response to the second selection-signal; and

first and second circuits each provided on the semiconductor substrate and each performing an operation, the operation of the first circuit being controlled by the first information, the operation of the second circuit being controlled by the second information.

10. The system as claimed in claim 9 , wherein

the controller further includes:

a plurality of first data terminals and a plurality of second data terminals;

the memory chip further including:

a plurality of third data terminals provided on the semiconductor substrate and being electrically coupled to the first data terminals of the controller, respectively; and

a plurality of fourth data terminals provided on the semiconductor substrate and being electrically coupled to the second data terminals of the controller, respectively;

the first and third data terminals communicating first data in response to the first selection-signal, the second and fourth data terminals communicating second data in response to the second selection-signal.

11. The system as claimed in claim 10 , wherein the first and second circuits are substantially same in configuration as each other.

12. The system as claimed in claim 11 , wherein the first and second circuits memorize the first and second data, respectively.

13. The system as claimed in claim 12 , wherein the first and second circuits respectively output the first and second data to the third and fourth data terminals substantially simultaneously with each other.

14. The system as claimed in claim 9 , wherein the operation includes at least one of a read operation of a corresponding one of the first and second circuits and a write operation of a corresponding one of the first and second circuits.

15. The system as claimed in claim 14 , wherein the read operation includes a refresh operation.

16. A system comprising:

a controller that includes first and second selection-signal terminals supplying first and second selection-signals, respectively; and

a memory chip that includes:

a semiconductor substrate;

third and fourth selection-signal terminals provided on the semiconductor substrate and being electrically coupled to the first and second selection-signal terminals of the controller to receive the first and second selection-signals, respectively;

first and second command circuits provided on the semiconductor substrate, the first command circuit latching a first command signal in response to the first selection-signal and the second command circuit latching a second command signal in response to the second selection-signal; and

first and second memory circuits provided on the semiconductor substrate, the first memory circuit performing an operation in response to the first command latched in the first command circuit and the second memory circuit performing an operation in response to the second command latched in the second command circuit.

17. The system as claimed in claim 16 , wherein the memory chip further includes first and second mode registers each provided on the semiconductor substrate, the first mode register storing first information in response to the first selection-signal, the second mode register storing second information in response to the second selection-signal.

18. The system as claimed in claim 17 , wherein the memory chip further includes first and second circuits each provided on the semiconductor substrate, the first and second circuits being substantially same in configuration as each other, the first and second circuits performing an operation in response to the information of the first and second mode registers, respectively.

19. The system as claimed in claim 17 , wherein

the controller further includes:

a plurality of first data terminals; and

a plurality of second data terminals; and

the memory chip further including:

a plurality of third data terminals provided on the semiconductor substrate and being electrically coupled to the first data terminals of the controller, respectively; and

a plurality of fourth data terminals provided on the semiconductor substrate and being electrically coupled to the second data terminals of the controller, respectively;

the first and third data terminals communicating first data in response to the first selection-signal, the second and fourth data terminals communicating second data in response to the second selection-signal.

20. The system as claimed in claim 19 , wherein the first and second circuits respectively memorize the first and second data, and respectively output the first and second data to the third and fourth data terminals substantially simultaneously with each other.