IP Library Granted Patent US 8,558,445
Granted Patent B2
US 8,558,445 · App. 13/594,035 · Granted Oct 15, 2013

EL display panel, EL display apparatus, and method of manufacturing EL display panel

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Quick Facts
Patent No.
US 8,558,445
App. No.
13/594,035
Granted
Oct 15, 2013
Kind
B2
Abstract

A light-emitting panel includes a thin film semiconductor that includes a thin film transistor. The thin film transistor includes a gate electrode, a semiconductor layer above the gate electrode, a gate insulating film between the gate electrode and the semiconductor layer, a first electrode electrically connected to the semiconductor layer, and a second electrode. A first interlayer insulating film is above the thin film semiconductor. A gate line and an auxiliary line are above the first interlayer insulating film and between the first interlayer insulating film and a second interlayer insulating film. The gate line is electrically connected to the gate electrode. An electroluminescence emitter includes two electrodes and a light-emitting layer between the two electrodes. One of the two electrodes is connected to the auxiliary line.

Claims (27)

1. A light-emitting panel, comprising:

a substrate;

a thin film semiconductor including a thin film transistor above the substrate, the thin film transistor including at least a gate electrode, a semiconductor layer above the gate electrode, a gate insulating film between the gate electrode and the semiconductor layer, a first electrode electrically connected to the semiconductor layer, and a second electrode;

a first interlayer insulating film above the thin film semiconductor;

a gate line above the first interlayer insulating film and electrically connected to the gate electrode;

an auxiliary line above the first interlayer insulating film;

a second interlayer insulating film above the gate line and the auxiliary line; and

an electroluminescence emitter including two electrodes and a light-emitting layer between the two electrodes, one of the two electrodes being connected to the auxiliary line,

wherein the gate line and the auxiliary line are between the first interlayer insulating film and the second interlayer insulating film.

2. The light-emitting panel according to claim 1 ,

wherein each of the auxiliary line and the gate line has a lower surface in contact with the first interlayer insulating film.

3. The light-emitting panel according to claim 1 ,

wherein the auxiliary line is side-by-side with the gate line.

4. The light-emitting panel according to claim 1 , further comprising:

a power supply line between the first interlayer insulating film and the second interlayer insulating film for supplying a driving current to the electroluminescence emitter.

5. The light-emitting panel according to claim 4 ,

wherein each of the power supply line and the gate line has a lower surface in contact with the first interlayer insulating film.

6. The light-emitting panel according to claim 4 ,

wherein the power supply line is side-by-side with the gate line.

7. The light-emitting panel according to claim 1 ,

wherein the thin film semiconductor includes a plurality of thin film transistors, and

the gate line is electrically connected to each of the plurality of thin film transistors via first conductive portions that pass through at least the first interlayer insulating film.

8. The light-emitting panel according to claim 7 ,

wherein a power supply line is electrically connected to each of the plurality of thin film transistors via second conductive portions that pass through at least the first interlayer insulating film in positions different than the first conductive portions.

9. The light-emitting panel according to claim 1 , further comprising:

a source line electrically connected to one of the first electrode and the second electrode,

wherein the source line is between the substrate and the first interlayer insulating film.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2025
From: JDI DESIGN AND DEVELOPMENT G.K.
To: MAGNOLIA BLUE CORPORATION
Reel/Frame 072039/0656 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2024
From: JOLED, INC.
To: JDI DESIGN AND DEVELOPMENT G.K.
Reel/Frame 066382/0619 →
CORRECTION BY AFFIDAVIT FILED AGAINST REEL/FRAME 063396/0671 Recorded Jun 12, 2023
From: JOLED, INC.
To: JOLED, INC.
Reel/Frame 064067/0723 →
SECURITY INTEREST Recorded Apr 20, 2023
From: JOLED, INC.
To: INCJ, LTD.
Reel/Frame 063396/0671 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 12, 2015
From: PANASONIC CORPORATION
To: JOLED INC
Reel/Frame 035187/0483 →