Semiconductor device having redundant word lines and redundant bit lines

1. A semiconductor device comprising:

a memory cell array that includes a plurality of word lines, a plurality of redundant word lines, a plurality of bit lines and a plurality of redundant bit lines, the memory cell array can be accessed by supplying a row address and a column address;

a row fuse circuit that stores addresses of a plurality of defective word lines included in the word lines;

a column fuse circuit that stores addresses of a plurality of defective bit lines included in the bit lines;

a row decoder that selects one of the word lines based on the row address when the row address does not match the addresses output from the row fuse circuit, and selects one of the redundant word lines when the row address matches one of the addresses output from the row fuse circuit; and

a column decoder that selects one of the bit lines based on the column address when the column address does not match the addresses output from the column fuse circuit, and selects one of the redundant bit lines when the column address matches one of the addresses output from the column fuse circuit, wherein

the memory cell array has a substantially rectangular shape having short sides in an extension direction of the word lines and the redundant word lines and having long sides in an extension direction of the bit lines and the redundant bit lines,

the row decoder, the row fuse circuit and the column fuse circuit are arranged along one of the long sides of the memory cell array, and are laid out in a direction of the short sides of the memory cell array, and

the column decoder is arranged along one of the short sides of the memory cell array.

2. The semiconductor device as claimed in claim 1 , wherein the column fuse circuit selectively outputs one or more of the addresses stored therein based on the row address.

3. The semiconductor device as claimed in claim 2 , wherein the row fuse circuit outputs all the addresses stored therein.

4. The semiconductor device as claimed in claim 1 , further comprising a comparison circuit that compares the addresses output from the column fuse circuit with the column address,

wherein the column fuse circuit includes a switching circuit that sequentially outputs two or more addresses stored therein to the comparison circuit.

5. The semiconductor device as claimed in claim 4 , wherein the comparison circuit is arranged along the long side of the memory cell array at near the short side of the memory cell array on which the column decoder is arranged.

6. The semiconductor device as claimed in claim 1 , wherein the row decoder, the row fuse circuit and the column fuse circuit are arranged in the direction of the short sides of the memory cell array in this order viewed from the one of the long sides of the memory cell array.

7. A semiconductor device comprising:

a memory cell array that includes a plurality of word lines, a plurality of bit lines, a plurality of redundant word lines each of which can replace one of the word lines and a plurality of redundant bit lines each of which can replace one of the bit lines, the memory cell array having a first side extending in a first direction and a second side extending in a second direction different from the first direction, the first side having a first length, and the second side having a second length different from the first length;

a row fuse circuit that stores one or more addresses of the word lines to be replaced with the redundant word lines, the row fuse circuit having substantially the first length in the first direction;

a column fuse circuit that stores one or more addresses of the bit lines to be replaced with the redundant bit lines, the column fuse circuit having substantially the first length in the first direction;

a row decoder that selects one of the word lines or one of the redundant word lines based on a row address, the row decoder having substantially the first length in the first direction; and

a column decoder that selects one of the bit lines or one of the redundant bit lines based on a column address, the column decoder having substantially the second length in the second direction.

8. The semiconductor device as claimed in claim 7 , wherein the row decoder, the row fuse circuit and the column fuse circuit are arranged in the second direction in this order viewed from the first side of the memory cell array.

9. The semiconductor device as claimed in claim 8 , further comprising a comparison circuit that compares the addresses output from the column fuse circuit with the column address.

10. The semiconductor device as claimed in claim 9 , wherein the row decoder, the row fuse circuit and the column fuse circuit are arranged between the memory cell array and the comparison circuit.

11. The semiconductor device as claimed in claim 10 , wherein the comparison circuit is arranged near the second side of the memory cell array.

12. The semiconductor device as claimed in claim 11 , wherein the column decoder is arranged along the second side of the memory cell array.

13. The semiconductor device as claimed in claim 12 , wherein the word line and the redundant word lines extend in the second direction, and the bit line and the redundant bit lines extend in the first direction.

14. A semiconductor device comprising:

a memory cell array that includes a plurality of word lines, a plurality of bit lines, a plurality of redundant word lines each of which can replace one of the word lines and a plurality of redundant bit lines each of which can replace one of the bit lines, the memory cell array having a first side extending in a first direction and a second side extending in a second direction different from the first direction;

a first fuse circuit that stores one or more addresses of one of the word lines and the bit lines to be replaced, the first fuse circuit having a first side extending in the first direction and a second side extending in the second direction, the first side of the first fuse circuit is longer than the second side of the first fuse circuit; and

a second fuse circuit that stores one or more addresses of the other of the word lines and the bit lines to be replaced, the second fuse circuit having a first side extending in the first direction and a second side extending in the second direction, the first side of the second fuse circuit is longer than the second side of the second fuse circuit.

15. The semiconductor device according to claim 14 , wherein the first side of the memory cell array is longer than the second side of the memory cell array.

16. The semiconductor device according to claim 14 , wherein the memory cell array, the first fuse circuit and the second fuse circuit are arranged in the second direction.

17. The semiconductor device according to claim 14 , further comprising a first decoder that selects one of the word lines or one of the redundant word lines based on a row address, the first decoder having a first side extending in the first direction and a second side extending in the second side, the first side of the first decoder is longer than the second side of the first decoder.

18. The semiconductor device according to claim 17 , wherein the first decoder is allocated between the first side of the memory cell array and the first side of the first fuse circuit.