Systems and methods for efficient memory access

1. A computer-implemented method of accessing data, comprising:

resetting a value of a register of a first processing core of a multi-core processor;

copying the bits of a compressed pointer into the lowest order bits of the register;

left shifting the register a predetermined number of bits;

executing on the first processing core a first instruction referencing memory at a virtual address specified by the register;

translating the virtual address into an identical physical address;

executing on a second processing core of the multi-core processor a second instruction referencing memory at the same virtual address referenced by the first instruction; and

translating the virtual address into an identical physical address;

wherein the first instruction and the second instruction both access the same physical memory location.

2. The method of claim 1 , wherein the compressed pointer is a thirty two bit value and the predetermined number of bits is three.

3. The method of claim 1 , wherein the virtual address is greater than or equal to 0x40000000.

4. The method of claim 1 , wherein the virtual address is less than 0x800000000.

5. A tangible, non-transitory computer-readable medium comprising instructions that when executed on a multi-core processor:

reset a value of a register of a first processing core of the processor;

copy the bits of a compressed pointer into the lowest order bits of the register;

left shift the register a predetermined number of bits;

execute on the first processing core a first instruction referencing memory at a virtual address specified by the register; and

translate the virtual address into an identical physical address; and

further comprising instructions that, when executed on a second processing core of the multi-core processor:

reference memory at the same virtual address referenced by the first instruction resulting in a translation of the virtual address into an identical physical address;

wherein the first instruction and second instruction both access the same physical memory location.

6. The medium of claim 5 , wherein the compressed pointer is a thirty two bit value and the predetermined number of bits is three.

7. The medium of claim 5 , wherein the virtual address is greater than or equal to 0x40000000.

8. The medium of claim 5 , wherein the virtual address is less than 0x800000000.

9. A computing system, comprising:

a multi-core processor comprising:

a first processing core controlled by a first operating system, and

a second processing core controlled by a second operating system; and

a physical memory comprising:

a first set of page tables associated with the first operating system,

a second set of page tables associated with the second operating system, and

instructions that when executed on the multi-core processor:

reset a value of a register of the first processing core of the processor;

copy the bits of a compressed pointer into the lowest order bits of the register;

left shift the register a predetermined number of bits; and

execute on the first processing core a first instruction referencing memory at a virtual address specified by the register;

execute on the second processing core of the processor a second instruction referencing memory at the same virtual address referenced by the first instruction;

wherein the first set of page tables map the virtual address to an identical physical address;

wherein the second set of page tables map the virtual address to an identical physical address; and

wherein the first instruction and second instruction both access the same physical memory location.

10. The system of claim 9 , wherein the compressed pointer is a thirty two bit value and the predetermined number of bits is three.

11. The system of claim 9 , wherein the virtual address is greater than or equal to 0x40000000.

12. The system of claim 9 , wherein the virtual address is less than 0x800000000.