IP Library Granted Patent US 9,921,954
Granted Patent B1
US 9,921,954 · App. 13/595,848 · Granted Mar 20, 2018

Method and system for split flash memory management between host and storage controller

Inventors: Erez Sabbag (Kiryat Tivon, IL); Hanan Weingarten (Hertzelia, IL)
Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
G06F12/0246
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Quick Facts
Patent No.
US 9,921,954
App. No.
13/595,848
Granted
Mar 20, 2018
Kind
B1
Abstract

A computer readable medium, a system and a method for flash memory device that my store instructions for receiving from a host computer a first command that is a write command of a first data unit to a flash memory device, receiving, from the host computer, a second command that is indicative of a manner in which at least one entity out of (a) memory management metadata, (b) the first data unit and (c) at least one other data unit, should be stored in the flash memory device, and programming the at least one entity in the flash memory device in response to the second command.

Claims (39)

1. A non-transitory computer readable medium that stores instructions for:

receiving, by a flash memory device, from a host computer and over an interface a first command that is a write command of a first data unit to the flash memory device; wherein the first command is a combination of a first physical address within the flash memory device and data;

receiving, by the flash memory device, from the host computer and over the interface, a second command that is indicative of a manner in which memory management metadata associated with the first data unit should be stored in the flash memory device; wherein the second command is a combination of a second address and the memory management metadata; and

programming, by the flash memory device, the memory management metadata and the first data unit in the flash memory device in response to both the first command and the second command,

wherein the programming, by the flash memory device, of the memory management metadata in the flash memory device in response to the second command occurs only if the second command is received immediately before the first command or is immediately received after the first command, and

wherein immediately refers to a time period between the receiving of the first command and the receiving of the second command during which the interface does not convey a different data unit that differs from the first data unit and is not associated with the memory management metadata.

2. The non-transitory computer readable medium according to claim 1 , wherein the first physical address is within a first block of the flash memory device; wherein second address is a second physical address that is within a second block of the flash memory device; wherein the second block differs from the first block; and

wherein the non-transitory computer readable medium stores instructions for storing the first data unit in a first flash memory buffer and storing the memory management metadata in a second flash memory buffer.

3. The non-transitory computer readable medium according to claim 1 , wherein the first physical address is within a block of the flash memory device;

wherein the second address is a second physical address that is within a second block of the flash memory device;

wherein the second block differs from the first block; and

wherein the non-transitory computer readable medium stores instructions for storing the first data unit and the memory management data at blocks of the flash memory device that differ from each other.

4. The non-transitory computer readable medium according to claim 1 , wherein the second address identifies the second command as a linked storage command that links a storage of the memory management metadata and the first data unit.

5. The non-transitory computer readable medium according to claim 1 , wherein the first command and the second command are sent over the interface using a format of a protocol that does not allow sending the memory management metadata attached to the data unit.

6. The non-transitory computer readable medium according to claim 1 , wherein the second command commands a concatenation of the first data unit and the memory management metadata.

7. The non-transitory computer readable medium according to claim 1 , wherein the second address belongs to a memory space that is not mapped to physical addresses of the flash memory device.

8. The non-transitory computer readable medium according to claim 1 , that stores instruction for ignoring the second command if a timing difference between the receiving of the second command and the receiving of the first command exceeds a timing threshold.

9. The non-transitory computer readable medium according to claim 1 , that stores instructions for programming the first data unit to a flash memory buffer that is managed at a different granularity than at least one other flash memory region of the flash memory device.

10. A method comprising:

receiving, by a flash memory device, from a host computer and over an interface a first command that is a write command of a first data unit to the flash memory device; wherein the first command is a combination of a first physical address within the flash memory device and data;

receiving, by the flash memory device, from the host computer and over the interface, a second command that is indicative of a manner in which memory management metadata associated with the first data unit should be stored in the flash memory device; wherein the second command is a combination of a second address and the memory management metadata; and

programming, by the flash memory device, the memory management metadata and the first data unit in the flash memory device in response to both the first command and the second command,

wherein the programming, by the flash memory device, of the memory management metadata in the flash memory device in response to both the first command and the second command occurs only if the second command is received immediately before the first command or is immediately received after the first command, and

wherein immediately refers to a time period between the receiving of the first command and the receiving of the second command during which the interface does not convey a different data unit that differs from the first data unit and is not associated with the memory management metadata.

11. The method according to claim 10 , wherein the first physical address is within a first block of the flash memory device; wherein the second address is a second physical address that is within a second block of the flash memory device; wherein the second block differs from the first block; and

wherein the method comprises storing the first data unit in a first flash memory buffer and storing the memory management metadata in a second flash memory buffer.

12. The method according to claim 10 , wherein the first physical address is within a block of the flash memory device; wherein the second address is a second physical address that is within a second block of the flash memory device; wherein the second block differs from the first block; and wherein the method storing the first data unit and the memory management metadata at blocks of the flash memory device that differ from each other.

13. The method according to claim 10 , wherein the second address identifies the second command as a linked storage command that links a storage of the memory management metadata and the first data unit.

14. The method according to claim 10 , wherein the first command and the second command are sent over the interface using a format of a protocol that does not allow sending the memory management metadata attached to the data unit.

15. The method according to claim 10 , wherein the second command commands a concatenation of the first data unit and the memory management metadata.

16. The method according to claim 10 , wherein the second address belongs to a memory space that is not mapped to physical addresses of the flash memory device.

17. The method according to claim 10 , comprising ignoring the second command if a timing difference between the receiving of the second command and the receiving of the first command exceeds a timing threshold.

18. The method according to claim 10 , comprising programming the first data unit to a flash memory buffer that is managed at a different granularity than at least one other flash memory region of the flash memory device.

19. A flash memory comprising:

an interface for receiving from a host computer a first command that is a write command of a first data unit to a flash memory device and for receiving, from the host computer, a second command that is indicative of a manner in which memory management metadata associated with the first data unit should be stored in the flash memory device; and

a programming circuit to program the memory management metadata and the first data unit in the flash memory device in response to both the first command and the second command; wherein the first command is a combination of a first physical address and data and the second command is a combination of a second address and the memory management metadata,

wherein the programming circuit programs the memory management metadata in the flash memory device in response to the first command and the second command only if the second command is received immediately before the first command or is immediately received after the first command, and

wherein immediately refers to a time period between the receiving of the first command and the receiving of the second command during which the interface does not convey a different data unit that differs from the first data unit and is not associated with the memory management metadata.

20. The flash memory according to claim 19 , wherein the first command and the second command are sent over the interface using a format of a protocol that does not allow sending the memory management metadata attached to the data unit.

Assignments (9)
MERGER Recorded Mar 3, 2023
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED; BROADCOM INTERNATIONAL PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 062952/0850 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2020
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
To: BROADCOM INTERNATIONAL PTE. LTD.
Reel/Frame 053771/0901 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047422 FRAME: 0464. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0702 →
MERGER Recorded Oct 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047422/0464 →
RELEASE OF SECURITY INTEREST Recorded Jan 11, 2017
From: KREOS CAPITAL IV (EXPERT FUND) LIMITED
To: DENSBITS TECHNOLOGIES LTD.
Reel/Frame 041339/0921 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 27, 2016
From: DENSBITS TECHNOLOGIES LTD.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 037622/0224 →
SECURITY INTEREST Recorded Mar 18, 2015
From: DENSBITS TECHNOLOGIES LTD.
To: KREOS CAPITAL IV (EXPERT FUND) LIMITED
Reel/Frame 035222/0547 →
SECURITY INTEREST Recorded Jul 30, 2014
From: DENSBITS TECHNOLOGIES LTD.
To: KREOS CAPITAL IV (EXPERT FUND) LIMITED
Reel/Frame 033444/0628 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 2, 2012
From: SABBAG, EREZ; WEINGARTEN, HANAN
To: DENSBITS TECHNOLOGIES LTD.
Reel/Frame 029389/0495 →