Semiconductor device using multi-phase clock signal and information processing system including the same

1. A semiconductor device comprising:

1 st to n th delay circuits cascade-connected in this order, the 1 st to n th delay circuits outputting 1 st to n th output clock signals, respectively, based on an input clock signal supplied to the 1 st delay circuit;

a control circuit controlling a delay amount of each of the 1 st to n th delay circuits such that the 1 st to n th output clock signals have different phases from one another; and

a data processing circuit processing a plurality of data signals synchronously with 1 st to n th output clock signals, respectively.

2. The semiconductor device as claimed in claim 1 , wherein a sum of the delay amounts of the 1 st to n th delay circuits is substantially the same as k clock cycles of the input clock signal, where k is an integer more than 1 and is different from n.

3. The semiconductor device as claimed in claim 2 , wherein a greatest common divisor of the n and the k is 1.

4. The semiconductor device as claimed in claim 3 , wherein the n is larger than the k.

5. The semiconductor device as claimed in claim 1 , wherein

the data processing circuit includes a plurality of input nodes and an output node,

each of the data signals is supplied to an associated one of the input nodes, and

the data processing circuit serially outputs the data signals to the output node synchronously with the 1 st to n th output clock signals.

6. The semiconductor device as claimed in claim 1 , wherein

the data processing circuit includes an input node and a plurality of output nodes,

the data signals are supplied in serial to the input node, and

the data processing circuit outputs each of the data signals to an associated one of the output nodes synchronously with the 1 st to n th output clock signals.

7. The semiconductor device as claimed in claim 2 , wherein

the data signals are n-bit data, and

when a greatest common divisor of the n and the k is GCM, the data processing circuit sequentially processing the n-hit data at each timing of a GCM/n cycle of the input clock signal.

8. A semiconductor device comprising:

a clock generating circuit including a plurality of delay circuits which are connected such that an output node of a preceding one of the delay circuits is connected to an input node of a succeeding one of the delay circuits and an input node of a leading one of the delay circuits being configured to receive an internal clock signal, the delay circuits being configured to respectively output delayed clock signals to the output nodes thereof, and the delayed clock signals outputted from the delay circuits being different in phase from one another; and

a data input/output circuit including a plurality of input nodes each supplied with corresponding data, an output node, and a plurality of switching circuits each provided between the output node and a corresponding one of the input nodes, each of the switching circuits being configured to transfer the corresponding data to the output node in response to a corresponding one of the delayed clock signals.

9. The semiconductor device as claimed in claim 8 , further comprising an external data terminal coupled to the data input/output circuit.

10. The semiconductor device as claimed in claim 8 , further comprising:

an additional data input/output circuit including a plurality of additional input nodes each supplied with additional corresponding data, an additional output node, and a plurality of additional switching circuits each provided between the additional output node and a corresponding one of the additional input nodes, each of the additional switching circuits being configured to transfer the additional corresponding data to the additional output node in response to the corresponding one of the delayed clock signals.

11. The semiconductor device as claimed in claim 10 , further comprising an additional external data terminal coupled to the additional data input/output circuit.

12. The semiconductor device as claimed in claim 8 , wherein the clock generating circuit further includes a delay control circuit configured to receive the internal clock signal and the delayed clock signal outputted from the output node of a lattermost one of the delay circuits, the delay control circuit being configured to adjust a delay amount of each of the delay circuits such that the internal clock signal and the delayed clock signal outputted from the output node of the lattermost one of the delay circuits are equal in phase to each other.

13. The semiconductor device as claimed in claim 8 , wherein the clock generating circuit further includes a shaping circuit configured to change a duty ratio of each of the delayed clock signals such that ones of high and low time periods of the delayed clock signal are not substantially overlapped with one another.

14. The semiconductor device as claimed in claim 12 , wherein the delay amount of each of the delay circuits is adjusted to take an equal value.

15. A semiconductor device comprising:

a delay line that includes n delay circuits cascade-connected and delays an input clock signal by k cycles; and

a routing circuit that generates multi-phase clock signals having different phases based on at least a part of n output clock signals output from the n delay circuits, respectively,

wherein the n and the k are both integers more than 1 and a greatest common divisor thereof is 1.

16. The semiconductor device as claimed in claim 15 , wherein the n is larger than the k.

17. The semiconductor device as claimed in claim 15 , wherein a phase interval of the multi-phase clock signals is smaller than a minimum delay time of each of the delay circuits.

18. The semiconductor device as claimed in claim 15 , further comprising:

a frequency dividing circuit that divides the input clock signal and an output clock signal output from the delay line by k to generate first and second divided clock signals, respectively; and

a control circuit that controls a delay amount of each of the n delay circuits based on phases of the first and second divided clock signals.