IP Library Granted Patent US 8,638,141
Granted Patent B1
US 8,638,141 · App. 13/599,496 · Granted Jan 28, 2014

Phase-locked loop

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Quick Facts
Patent No.
US 8,638,141
App. No.
13/599,496
Granted
Jan 28, 2014
Kind
B1
Abstract

A phase-locked loop for generating an output signal including a signal generator arranged to generate an output, a comparison unit arranged to compare the output with a reference signal so as to provide a digital signal, and a loop filter arranged to generate a control signal for controlling the signal generator in dependence on the digital signal. The loop filter includes a proportional path having a digital filter arranged to generate a first component of the control signal for controlling the phase of the output generated by the signal generator, and an analogue integral path arranged to generate a second component of the control signal for controlling the frequency of the output generated by the signal generator.

Claims (28)

1. A phase-locked loop for generating an output signal comprising:

a signal generator arranged to generate the output signal;

a comparison unit arranged to compare the output signal with a reference signal so as to provide a digital signal;

a loop filter arranged to generate a control signal for controlling the signal generator in dependence on the digital signal, the loop filter comprising:

a proportional path comprising a digital filter arranged to generate a first component of the control signal for controlling the phase of the output signal generated by the signal generator; and

an analogue integral path arranged to generate a second component of the control signal for controlling the frequency of the output signal generated by the signal generator.

2. A phase-locked loop as claimed in claim 1 , wherein the digital filter comprises a finite impulse response filter.

3. A phase-locked loop as claimed in claim 2 , wherein the integral path comprises a charge pump and an integrator.

4. A phase-locked loop as claimed in claim 3 , wherein the integrator comprises a capacitor.

5. A phase-locked loop as claimed in claim 1 , wherein the integral path comprises a charge pump and an integrator.

6. A phase-locked loop as claimed in claim 5 , wherein the integrator comprises a capacitor.

7. A phase-locked loop as claimed in claim 1 , wherein the comparison unit comprises a binary phase detector.

8. A phase-locked loop as claimed in claim 7 , wherein the comparison unit is arranged to sample the output signal at a rate, the frequency of the output being dependent on said rate.

9. A phase-locked loop as claimed in claim 8 , said rate being dependent on a rate control signal.

10. A phase-locked loop as claimed in claim 1 , wherein the comparison unit is arranged to sample the output signal at a rate, the frequency of the output being dependent on said rate.

11. A phase-locked loop as claimed in claim 10 , said rate being dependent on a rate control signal.

12. A phase-locked loop as claimed in claim 1 , wherein the frequency of the reference signal is greater than 1 GHz.

13. A phase-locked loop as claimed in claim 1 , wherein the signal generator comprises a ring oscillator.

14. A phase-locked loop as claimed in claim 1 , wherein the signal generator includes a divider arranged to receive and frequency divide the output signal from the signal generator, the output signal being the said divided output.

15. A circuit comprising:

a phase-locked loop according to claim 1 ; and

an amplifier having a modulation bandwidth, wherein the bandwidth of the phase-locked loop is greater than the modulation bandwidth of the amplifier.

16. A method for generating an output signal comprising:

generating the output signal at a signal generator;

comparing the output signal with a reference signal so as to provide a digital signal;

at a loop filter, generating a control signal for controlling the signal generator in dependence on the digital signal, the loop filter comprising:

a proportional path comprising a digital filter to generate a first component of the control signal for controlling the phase of the output signal generated by the signal generator; and

an analogue integral path to generate a second component of the control signal for controlling the frequency of the output signal generated by the signal generator.

Assignments (2)
CHANGE OF NAME Recorded Sep 22, 2015
From: CAMBRIDGE SILICON RADIO LIMITED
To: QUALCOMM TECHNOLOGIES INTERNATIONAL, LTD.
Reel/Frame 036663/0211 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 4, 2012
From: LAMANNA, PASQUALE; SORNIN, NICOLAS; ORIFIAMMA, DAVIDE; PAVAO MOREIRA, CRISTIAN
To: CAMBRIDGE SILICON RADIO LIMITED
Reel/Frame 028891/0240 →