IP Library Granted Patent US 8,879,671
Granted Patent B2
US 8,879,671 · App. 13/599,943 · Granted Nov 4, 2014

Worker and iteration control for parallel turbo decoder

Inventors: Axel Huebner (Munich, DE); Jens Berkmann (Munich, DE); Maria Fresia (Munich, DE); Armin Hautle (Dachau, DE)
Assignee: Intel Mobile Communications GmbH
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Quick Facts
Patent No.
US 8,879,671
App. No.
13/599,943
Granted
Nov 4, 2014
Kind
B2
Abstract

A device such as a worker, window-size and iteration control unit (WWICU) is proposed. The WWICU determines processing, iteration, and window information based on format information indicative of one or more formats to be processed by a decoding process. The processing information may include a number of parallel workers, the iteration information may include a number of half-iterations, and the window information may include a window size to be used in the decoding process. The WWICU then determines time information including a total cycle count based on the processing information, the iteration information, and the window information. In response to determining that the total cycle count is not beyond a threshold value, the WWICU may transmit configuration information including the processing, iteration, and window information to a device, such as a turbo decoding device, configurable to perform the decoding process based on the configuration information.

Claims (57)

1. A device, comprising:

a processor; and

a non-transitory memory operatively coupled to the processor and storing computer readable instructions that, when executed by the processor, cause the device to:

determine iteration information based on format information indicative of one or more formats to be processed by a decoding process, wherein the iteration information includes a number of half-iterations to be used in the decoding process;

determine window information based on the format information, wherein the window information includes a window size to be used in the decoding process;

determine time information based on the iteration information and the window information, wherein the time information includes a total cycle count; and

transmit configuration information to a decoding device configurable to perform the decoding process based on the configuration information, wherein the configuration information includes the iteration information and the window information.

2. The device of claim 1 , wherein the non-transitory memory further stores computer readable instructions that, when executed by the processor, cause the device to:

determine processing information based on the format information, wherein the processing information includes a number of parallel workers to be used in the decoding process; and

determine the time information based on the processing information, the iteration information, and the window information,

wherein the configuration information further includes the processing information.

3. The device of claim 1 , wherein the non-transitory memory further stores computer readable instructions that, when executed by the processor, cause the device to:

determine whether the total cycle count is beyond a threshold value; and

in response to determining that the total cycle count is not beyond the threshold value, transmit the configuration information to the decoding device.

4. The device of claim 3 , wherein the non-transitory memory further stores computer readable instructions that, when executed by the processor, cause the device to:

in response to determining that the total cycle count is beyond the threshold value,

iteratively decrease the number of half-iterations, and

iteratively determine the total cycle count until the total cycle count is less than or equal to the threshold value.

5. The device of claim 1 , wherein the non-transitory memory further stores computer readable instructions that, when executed by the processor, cause the device to:

determine the total cycle count by determining a sum of one or more cycle counts corresponding to each of the one or more formats.

6. The device of claim 1 , wherein the configuration information includes instructions that, when executed by the decoding device, cause the decoding device to be configured in accordance with the configuration information.

7. The device of claim 6 , wherein the non-transitory memory further stores computer readable instructions that, when executed by the processor, cause the device to:

update a database of configuration information based on the configuration information by storing the configuration information in association with the one or more formats.

8. The device of claim 6 , wherein the one or more formats are based on multiple stream reception, and wherein the one or more formats include one or more of a Long Term Evolution (LTE) format, a High-Speed Downlink Packet Access (HSDPA) format, and a Time Division Synchronous Code Division Multiple Access (TD-SCDMA) format.

9. A device, comprising:

a processor; and

a non-transitory memory operatively coupled to the processor and storing computer readable instructions that, when executed by the processor, cause the device to:

receive format information corresponding to a format to be processed by a decoding process;

determine a number of half-iterations to be used in the decoding process based on a database of configuration information, wherein the database of configuration information includes the format stored in association with the number of half-iterations;

determine a window size to be used in the decoding process based on the database of configuration information, wherein the database of configuration information includes the format stored in association with the window size; and

transmit configuration information to a decoding device configurable to perform the decoding process based on the configuration information, wherein the configuration information includes the number of half-iterations and the window size.

10. The device of claim 9 , wherein the decoding process is an iterative decoding process.

11. The device of claim 9 , wherein the format is a Long Term Evolution (LTE) format.

12. The device of claim 9 , wherein the format is a High-Speed Downlink Packet Access (HSDPA) format.

13. The device of claim 9 , wherein the format is a Time Division Synchronous Code Division Multiple Access (TD-SCDMA) format.

14. The device of claim 9 , wherein the configuration information includes instructions that, when executed by the decoding device, cause the decoding device to be configured in accordance with the configuration information.

15. The device of claim 9 , wherein the non-transitory memory further stores computer readable instructions that, when executed by the processor, cause the device to:

update the database of configuration information.

16. The device of claim 9 , wherein the non-transitory memory further stores computer readable instructions that, when executed by the processor, cause the device to:

determine a number of parallel workers to be used in the decoding process based on the database of configuration information, wherein the database of configuration information includes the format stored in association with the number of parallel workers,

wherein the configuration information further includes the number of parallel workers.

17. A method comprising:

determining, by a first device, iteration information based on format information indicative of one or more formats to be processed by a decoding process, wherein the iteration information includes a number of half-iterations to be used in the decoding process;

determining, by the first device, window information based on the format information, wherein the window information includes a window size to be used in the decoding process;

determining, by the first device, time information based on the iteration information and the window information, wherein the time information includes a total cycle count; and

transmitting, by the first device, configuration information to a second device configurable to perform the decoding process based on the configuration information, wherein the configuration information includes the iteration information and the window information.

18. The method of claim 17 , wherein the decoding process is a turbo decoding process, and wherein the second device is a turbo decoding device.

19. The method of claim 17 , further comprising:

determining, by the first device, processing information based on the format information, wherein the processing information includes a number of parallel workers to be used in the decoding process; and

determining, by the first device, the time information based on the processing information, the iteration information, and the window information,

wherein the configuration information further includes the processing information.

20. The method of claim 19 , further comprising:

determining, by the first device, whether the total cycle count is beyond a threshold value;

in response to determining that the total cycle count is not beyond the threshold value, transmitting the configuration information to the second device; and

in response to determining that the total cycle count is beyond the threshold value, iteratively increasing, by the first device, the number of parallel workers,

iteratively decreasing, by the first device, the number of half-iterations, and

iteratively determining, by the first device, the total cycle count until the total cycle count is less than or equal to the threshold value.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 29, 2022
From: INTEL DEUTSCHLAND GMBH
To: INTEL CORPORATION
Reel/Frame 061356/0001 →
CHANGE OF NAME Recorded Nov 6, 2015
From: INTEL MOBILE COMMUNICATIONS GMBH
To: INTEL DEUTSCHLAND GMBH
Reel/Frame 037057/0061 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 10, 2013
From: HUEBNER, AXEL; BERKMANN, JENS; FRESIA, MARIA; HAEUTLE, ARMIN
To: INTEL MOBILE COMMUNICATIONS GMBH
Reel/Frame 030764/0736 →
Continuity (1)
Related Publication 20140064413A1 · Mar 6, 2014