IP Library Granted Patent US 8,866,196
Granted Patent B2
US 8,866,196 · App. 13/600,087 · Granted Oct 21, 2014

Programmable substrate and applications thereof

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,866,196
App. No.
13/600,087
Granted
Oct 21, 2014
Kind
B2
Abstract

An integrated circuit die includes a semiconductor substrate and a plurality of electronic circuits on the semiconductor substrate. The semiconductor substrate is divided into a plurality of regions. A first region of the substrate supports a first type of electronic circuit and has first permittivity, permeability, and conductivity characteristics. A second region of the substrate supports a second type of electronic circuit and has second permittivity, permeability, and conductivity characteristics.

Claims (70)

1. An integrated circuit die comprises:

a semiconductor substrate; and

a plurality of electronic circuits on the semiconductor substrate, wherein the semiconductor substrate is divided into a plurality of regions, wherein a first region of the plurality of regions supports a first type of electronic circuit and the semiconductor substrate has first permittivity, permeability, and conductivity characteristics within the first region and wherein a second region of the plurality of regions supports a second type of electronic circuit and the semiconductor substrate has second permittivity, permeability, and conductivity characteristics within the second region, wherein the semiconductor substrate in the first region includes a substrate material that has a perforated silicon pattern such that first region has a high effective permittivity.

2. The integrated circuit die of claim 1 , wherein the semiconductor substrate comprises at least one of:

silicon germanium;

porous alumina;

silicon monocrystals; and

gallium arsenide.

3. The integrated circuit die of claim 1 further comprises:

the semiconductor substrate in the first region including a substrate material that has embedded therein a first embedding pattern of at least one of metallic inclusions and dielectric elements to produce the first permittivity, permeability, and conductivity characteristics; and

the semiconductor substrate in the second region including the substrate material that has embedded therein a second embedding pattern of the at least one of metallic inclusions and dielectric elements to produce the second permittivity, permeability, and conductivity characteristics.

4. The integrated circuit die of claim 3 further comprises:

the first embedding pattern indicating a first quantity of the at least one of metallic inclusions and dielectric elements, a first spacing for the at least one of metallic inclusions and dielectric elements, and a first variety of sizes for the at least one of metallic inclusions and dielectric elements; and

the second embedding pattern indicating a second quantity of the at least one of metallic inclusions and dielectric elements, a second spacing for the at least one of metallic inclusions and dielectric elements, and a second variety of sizes for the at least one of metallic inclusions and dielectric elements.

5. The integrated circuit die of claim 1 further comprises:

the semiconductor substrate in the first region including a substrate material that has embedded therein metallodielectric structures such that the first region has a high effective permeability.

6. The integrated circuit die of claim 1 , wherein an electronic circuit of the plurality of electronic components comprises at least one of:

a capacitor;

a resistor;

an inductor;

a transistor;

a diode; and

an antenna.

7. A semiconductor substrate comprises:

a plurality of regions, wherein a first region of the plurality of regions has first permittivity, permeability, and conductivity characteristics and wherein a second region of the plurality of regions has second permittivity, permeability, and conductivity characteristics, wherein in the first region, a substrate material that has a perforated silicon pattern such that first region has a high effective permittivity.

8. The semiconductor substrate of claim 7 comprises a material of at least one of:

silicon germanium;

porous alumina;

silicon monocrystals; and

gallium arsenide.

9. The semiconductor substrate of claim 7 further comprises:

in the first region, a substrate material that has embedded therein a first embedding pattern of at least one of metallic inclusions and dielectric elements to produce the first permittivity, permeability, and conductivity characteristics; and

in the second region, the substrate material that has embedded therein a second embedding pattern of the at least one of metallic inclusions and dielectric elements to produce the second permittivity, permeability, and conductivity characteristics.

10. The semiconductor substrate of claim 9 further comprises:

the first embedding pattern indicating a first quantity of the at least one of metallic inclusions and dielectric elements, a first spacing for the at least one of metallic inclusions and dielectric elements, and a first variety of sizes for the at least one of metallic inclusions and dielectric elements; and

the second embedding pattern indicating a second quantity of the at least one of metallic inclusions and dielectric elements, a second spacing for the at least one of metallic inclusions and dielectric elements, and a second variety of sizes for the at least one of metallic inclusions and dielectric elements.

11. The semiconductor substrate of claim 7 further comprises:

in the first region, a substrate material that has embedded therein metallodielectric structures such that the first region has a high effective permeability.

12. The semiconductor substrate of claim 7 further comprises:

a third region of the plurality of regions having third permittivity, permeability, and conductivity characteristics.

13. The semiconductor substrate of claim 7 further comprising a plurality of electronic components including at least one of:

a capacitor;

a resistor;

an inductor;

a transistor;

a diode; and

an antenna.

14. A semiconductor substrate comprises:

a plurality of regions, wherein:

a first region of the plurality of regions has first permittivity, permeability, and conductivity characteristics, formed of a substrate material that has embedded therein a first embedding pattern of at least one of metallic inclusions and dielectric elements to produce the first permittivity, permeability, and conductivity characteristics, the first embedding pattern indicating a first quantity of the at least one of metallic inclusions and dielectric elements, a first spacing for the at least one of metallic inclusions and dielectric elements, and a first variety of sizes for the at least one of metallic inclusions and dielectric elements; and

a second region of the plurality of regions has second permittivity, permeability, and conductivity characteristics, formed of a substrate material that has embedded therein a second embedding pattern of the at least one of metallic inclusions and dielectric elements to produce the second permittivity, permeability, and conductivity characteristics, the second embedding pattern indicating a second quantity of the at least one of metallic inclusions and dielectric elements, a second spacing for the at least one of metallic inclusions and dielectric elements, and a second variety of sizes for the at least one of metallic inclusions and dielectric elements.

15. The semiconductor substrate of claim 14 comprises a material of at least one of:

silicon germanium;

porous alumina;

silicon monocrystals; and

gallium arsenide.

16. The semiconductor substrate of claim 14 further comprises:

in the first region, a substrate material that has embedded therein metallodielectric structures such that the first region has a high effective permeability.

17. The semiconductor substrate of claim 14 further comprises:

in the first region, a substrate material that has a perforated silicon pattern such that first region has a high effective permittivity.

18. The semiconductor substrate of claim 14 further comprises:

a third region of the plurality of regions having third permittivity, permeability, and conductivity characteristics.

19. The semiconductor substrate of claim 14 further comprising a plurality of electronic components formed in the first region and the second region.

20. The semiconductor substrate of claim 19 , wherein the plurality of electronic components comprises at least one of:

a capacitor;

a resistor;

an inductor;

a transistor;

a diode; and

an antenna.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE PATENT NUMBER 9,385,856 TO 9,385,756 PREVIOUSLY RECORDED AT REEL: 47349 FRAME: 001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 22, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 051144/0648 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE PREVIOUSLY RECORDED ON REEL 047229 FRAME 0408. ASSIGNOR(S) HEREBY CONFIRMS THE THE EFFECTIVE DATE IS 09/05/2018. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047349/0001 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047229/0408 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 31, 2012
From: ALEXOPOULOS, NICOLAOS G.
To: BROADCOM CORPORATION, A CALIFORNIA CORPORATION
Reel/Frame 028881/0470 →