IP Library Granted Patent US 9,076,820
Granted Patent B2
US 9,076,820 · App. 13/600,373 · Granted Jul 7, 2015

Method for manufacturing semiconductor device and semiconductor device

Inventors: Soichiro Kitazaki (Mie-ken, JP); Masaru Kidoh (Mie-ken, JP); Mitsuru Sato (Mie-ken, JP); Ryota Katsumata (Mie-ken, JP); Tadashi Iguchi (Mie-ken, JP)
Assignee: Kabushiki Kaisha Toshiba
H01L29/66666H01L29/7827H01L27/11582H01L27/11565
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Quick Facts
Patent No.
US 9,076,820
App. No.
13/600,373
Granted
Jul 7, 2015
Kind
B2
Abstract

According to one embodiment, a method for manufacturing a semiconductor device includes forming a plurality of insulating isolation sections provided so as to extend in a first direction, isolate the stacked body in a second direction, and have a projection projecting from the stacked body. Each insulating isolation section has a side wall including recessed sections and projected sections repeated along the first direction. The method includes forming a sidewall film on a side wall of the projection of the insulating isolation section, and forming a plurality of first holes surrounded by the sidewall film and isolated by the sidewall film in the first direction, between the plurality of insulating isolation sections. The method includes forming a second hole in the stacked body provided under the first hole by etching with the insulating isolation section and the sidewall film used as a mask.

Claims (25)

1. A semiconductor device comprising:

a substrate;

a first stacked body having a plurality of electrode layers and a plurality of insulating layers alternately stacked on the substrate;

a second stacked body including a select gate provided on the first stacked body;

a plurality of insulating isolation sections provided so as to extend in a first direction, and isolate the first stacked body and the second stacked body in a second direction perpendicular to the first direction, in which each of the insulating isolation sections has a side wall having recessed sections and projected sections repeated along the first direction in a planar view taken from a direction vertical to a main face of the substrate;

a first channel body provided in a first hole penetrating the second stacked body and the first stacked body;

a first memory film including a first charge storage film provided between the first channel body and a side wall of the first hole; and

an insulating sidewall film provided between the first memory film and each of the insulating isolation sections above the select gate, the insulating sidewall film extending along the first direction in a planar view taken from the direction vertical to the main face of the substrate, a permittivity of the insulating sidewall film being higher than a permittivity of a silicon oxide film,

the first channel body having a column-shaped section provided under a region surrounded by the insulating sidewall film between the plurality of insulating isolation sections, and isolated by the insulating sidewall film in the first direction.

2. The device according to claim 1 , wherein the insulating sidewall film is a silicon nitride film.

3. The device according to claim 1 , wherein the insulating sidewall film is an aluminum oxide film.

4. The device according to claim 1 , wherein the insulating sidewall film is a hafnium oxide film.

5. The device according to claim 1 , wherein the insulating sidewall film is a hafnium aluminate film.

6. The device according to claim 1 , wherein the side wall of the insulating isolation section is formed into a shape of a curved line along the first direction.

7. The device according to claim 1 , wherein a pair of the column-shaped sections is connected in a lower part of the stacked body.

8. The device according to claim 1 , wherein

the first channel body has an impurity diffusion region provided in a neighborhood of an upper end of the select gate, and

the impurity diffusion region has an impurity concentration higher than an impurity concentration of a lower part of the impurity diffusion region in the first channel body.

9. The device according to claim 1 , further comprising:

a second channel body provided in a second hole penetrating the second stacked body and the first stacked body, the first channel body and the second cannel body being arranged in the first direction; and

a second memory film including a second charge storage film provided between the second channel body and a side wall of the second hole,

the insulating sidewall film extending from a first portion between the first memory film and each of the insulating isolation sections to a second portion between the second memory film and each of the insulating isolation sections.

10. The device according to claim 1 , wherein the insulating sidewall film is overlapped with the select gate in the planar view taken from the direction vertical to the main face of the substrate.

11. The device according to claim 10 , wherein the insulating sidewall film is provided in direct contact with a top face of the select gate.

12. The device according to claim 1 , wherein the insulating sidewall film is provided in direct contact with each of the insulating isolation sections.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 6, 2012
From: KITAZAKI, SOICHIRO; KIDOH, MASARU; SATO, MITSURU; KATSUMATA, RYOTA; IGUCHI, TADASHI
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 029244/0129 →
Priority Claims (1)
JP 2012-041993 · Feb 28, 2012 · national
Continuity (1)
Related Publication 20130228852A1 · Sep 5, 2013