High read speed memory with gate isolation
View Patent ↗Providing for a serial array memory transistor architecture that achieves high read speeds compared with conventional serial array memory is described herein. By way of example, the serial array memory can be connected to and can drive a gate voltage of a small capacitance pass transistor, to facilitate sensing memory transistors of the serial array. The pass transistor modulates current flow or voltage at an adjacent metal bitline, which can be utilized to sense a program or erase state(s) of the memory transistors. Due to the small capacitance of the pass transistor, read latency for the serial array can be significantly lower than conventional serial array memory (e.g., NAND memory). Further, various mechanisms for forming an amplifier region of the serial array memory comprising discrete pass transistor are described to facilitate efficient fabrication of the serial array memory transistor architecture.
1. Electronic memory, comprising:
a serial array of memory transistors connected at one end of the serial array to a gate of a pass transistor;
an electrical contact that connects a metal bitline of the electronic memory to a source or drain of the pass transistor, wherein:
the gate of the pass transistor is a discreet segment of a semiconductor architecture that is isolated from a neighboring gate of a neighboring pass transistor; and
a sensing circuit connected to the metal bitline.
2. The electronic memory of claim 1 , the gate of the pass transistor is isolated within the semiconductor architecture with a self-aligned poly process.
3. The electronic memory of claim 1 , the gate of the pass transistor is isolated within the semiconductor architecture with a dedicated patterning process.
4. The electronic memory of claim 1 , the pass transistor having a channel region that is isolated within the semiconductor architecture by a masking process that prevents or mitigates implantation of dopants into the channel region.
5. The electronic memory of claim 1 , the pass transistor having a channel region that is isolated within the semiconductor architecture by an etching process that removes dopants from the channel region.
6. The electronic memory of claim 1 , the pass transistor having a channel region that is isolated within the semiconductor architecture by a reverse doping process that compensates dopants in the channel region.
7. The electronic memory of claim 1 , wherein a current flowing along the serial array activates or deactivates the pass transistor via the pass transistor gate.
8. The electronic memory of claim 7 , wherein the sensing circuit is configured to detect enabling or disabling of the pass transistor.
9. The electronic memory of claim 8 , wherein the sensing circuit detects the enabling or the disabling of the pass transistor by sensing a read current or lack of read current, respectively, at the metal bitline.
10. The electronic memory of claim 1 , further comprising a second array of transistors arranged electrically in serial, the second array having one end connected to the metal bitline and having another end connected to a gate of a second pass transistor.
11. The electronic memory of claim 10 , the second pass transistor modulates current or voltage of another metal bitline of the electronic memory that is connected to a source or drain of the second pass transistor.
12. A method for operating an electronic memory device, comprising:
selecting a serial array of the electronic memory device for a read operation;
apply a wordline read voltage to a wordline of a selected transistor of the serial array;
apply a bitline read voltage to a metal bitline connected to a first end of the serial array;
sensing at least one of a voltage or a current of a second metal bitline, other than the metal bitline, for determining a state of the selected transistor.
13. The method of claim 12 , further comprising precharging the metal bitline to facilitate preparing the serial array for the applying the read voltage to the metal bitline.
14. The method of claim 12 , further comprising increasing voltage of a second wordline connected to a non-selected transistor of the serial array.
15. The method of claim 12 , further comprising increasing voltage of a plurality of wordlines connected respectively to a plurality of non-selected transistors of the serial array.
16. The method of claim 12 , further comprising sensing the metal bitline for determining a state of an additional transistor connected to a second serial array of the electronic memory device for a further read operation.
17. A system for operating an electronic memory, comprising:
means for selecting a serial array of the electronic memory for a read operation;
means for applying a select read voltage to a wordline of a selected transistor of the serial array;
means for applying an activation read voltage to a metal bitline connected to a first end of the serial array; and
means for sensing at least one of a current flow or a voltage at a pass transistor via a second metal bitline in response to applying the activation read voltage to the metal bitline.
18. The system of claim 17 , further comprising means for precharging the metal bitline in preparation for the read operation.
19. The system of claim 17 , further comprising means for boosting voltage of one or more additional wordlines connected respectively to additional transistors on the serial array.
20. The system of claim 17 , further comprising means for determining a program or erase state of the selected transistor as a function of at least one of current flow or voltage sensed at the pass transistor via the second metal bitline.