Multi-port memory based on DRAM core
View Patent ↗A semiconductor memory device includes a plurality of N external ports, each of which receives commands, and an internal circuit which performs at least N access operations during a minimum interval of the commands that are input into one of the external ports.
1. A multi-port memory, comprising:
a plurality of memory cores having memory cells;
a plurality of input/output ports, each of which includes a clock terminal configured to receive a clock signal, address terminals configured to receive address signals that are supplied in synchronization with the clock signal for selecting the memory cells, and data input/output terminals configured to input and output data signals; and
a plurality of control circuits, each of which is provided for a corresponding one of the plurality of memory cores, and selects the address signals supplied from the address terminals of one of the input/output ports to access the memory cells indicated by the selected address signals,
wherein when address signals indicating a same memory core of the plurality of memory cores are input into two or more of the input/output ports, a control circuit corresponding to the same memory core makes the same memory core operate in an order in which the address signals are received.
2. The multi-port memory, as claimed in claim 1 , wherein each of the input/output ports includes a command terminal configured to receive a command signal in synchronization with the clock signal for controlling operations of the plurality of memory cores, and wherein each said command signal input into one of the input/output ports for activating the plurality of memory cores is supplied at intervals twice or more times longer than a operation period of the plurality of memory cores required for a read operation and a write operation.
3. The multi-port memory as claimed in claim 2 , wherein the command signal is invalidated if when each said command signal is input into one of the input/output ports without securing the intervals.
4. The multi-port memory as claimed in claim 2 , wherein each said command signal that is input at intervals shorter than twice the operation period is accepted when said each said command is input to different ones the input/output ports.
5. The multi-port memory as claimed in claim 1 , further comprising a buffer configured to store therein data the memory cells, wherein the data read from or written in the memory cells are transferred via the buffer between the memory cells and the data input/output terminals.
6. The multi-port memory as claimed in claim 1 , wherein each of the input/output ports includes a command terminal configured to receive a command signal in synchronization with the clock signal for controlling operations of the plurality of memory cores.
7. The multi-port memory as claimed in claim 6 , wherein, for a read operation and a write operation, the command terminal receives an active command for activating a specific memory area of the plurality of memory cores and an action command indicative of either the read operation or the write operation with respect to the specific memory area.
8. The multi-port memory as claimed in claim 7 , wherein the address terminals receive the address signals for selecting the specific memory area in the plurality of memory cores and the address signals for selecting the memory cells in the specific memory area in conjunction with the active command and the action command, respectively.
9. The multi-port memory as claimed in claim 1 , wherein the memory cells include capacitors configured to store therein electric charge responding to values of the data signals.
10. The multi-port memory as claimed in claim 9 , wherein the memory cells are connected to bit lines for inputting and outputting the data signals, and a precharge operation for resetting the bit lines to a precharge voltage is automatically performed after a read operation and a write operation.
11. A method of controlling a multi-port memory that includes:
a plurality of memory cores having memory cells;
a plurality of input/output ports, each of which includes a clock terminal configured to receive a clock signal, address terminals configured to receive address signals that are supplied in synchronization with the clock signal for selecting the memory cells, and data input/output terminals for configured to input and output data signals; and
a plurality of control circuits, each of which is provided for a corresponding one of the plurality of memory cores, and selects the address signals supplied from the address terminals of one of the input/output ports to access the memory cells indicated by the selected address signals,
said the method comprising a step of,
when the address signals indicating a same memory core of the plurality of memory cores are input into two or more of the input/output ports, making the same memory core operate under control of the control circuit corresponding to the same memory core in an order in which the address signals are received.
12. The method as claimed in claim 11 , further comprising a step of receiving command signals for activating the plurality of memory cores by each of the input/output ports at intervals twice or more times longer than a operation period of the plurality of memory cores required for a read operation and a write operation.
13. The method as claimed in claim 12 , further comprising a step of invalidating the command signals when the command signals are input into one of the input/output ports without securing the intervals.