Impedance calibration circuit

1. An impedance calibration circuit, comprising:

a first reference voltage generator configured to generate a first reference voltage in response to reference voltage calibration signals;

a second reference voltage generator configured to provide a second reference voltage as a conversion voltage;

an impedance calibration signal generator configured to compare the conversion voltage with the first reference voltage and generate impedance calibration signals when an enable signal, connected to the impedance calibration signal generator, is activated; and

a register configured to store the impedance calibration signals finally calibrated and generate the reference voltage calibration signals in response to the stored impedance calibration signals.

2. The impedance calibration circuit according to claim 1 , further comprising a signal combination unit coupled to the impedance calibration signal generator for generating the enable signal and configured to activate the enable signal responsive to an activation of any one of a reference voltage calibration enable signal and an impedance calibration enable signal.

3. The impedance calibration circuit according to claim 2 , wherein the signal combination unit includes a NAND gate and an inverter.

4. The impedance calibration circuit according to claim 2 , wherein the reference voltage calibration enable signal is activated when a power-up signal is activated and when the impedance calibration enable signal is activated.

5. The impedance calibration circuit according to claim 1 , wherein the first reference voltage generator comprises:

a plurality of transistors connected to a power supply terminal,

a plurality of logic gates configured to selectively operate the plurality of transistors in response to the reference voltage calibration signals, and

a plurality of resistors connected between the plurality of transistors and a ground terminal.

6. The impedance calibration circuit according to claim 5 , wherein the plurality of logic gates are NOR gates configured to select the plurality of transistors in response to respective reference voltage calibration signals when a control signal is activated.

7. The impedance calibration circuit according to claim 5 , wherein the plurality of transistors connected to a power supply terminal are NMOS transistors.

8. The impedance calibration circuit according to claim 5 , wherein the plurality of transistors are designed to have different sizes.

9. The impedance calibration circuit according to claim 5 , wherein each of the plurality of transistors have a different size.

10. The impedance calibration circuit according to claim 1 , wherein the impedance calibration signal generator comprises:

a comparator configured to compare the conversion voltage with the first reference voltage and generate an output signal corresponding to a result of the comparison,

a code generator configured to increase or decrease a value of the impedance calibration signals in response to the output signal of the comparator, and

a first driver configured to distribute an external voltage at a distribution ratio of a calibrated internal resistance value of the first driver and a resistance value of an external resistor in response to the impedance calibration signals and output a distributed voltage as the conversion voltage.

11. The impedance calibration circuit according to claim 10 , wherein the first driver is a PMOS driver.

12. The impedance calibration circuit according to claim 10 , wherein the impedance calibration signal generator comprises:

a second comparator configured to compare a second conversion voltage with the first reference voltage and generate an output signal corresponding to a result of the comparison,

a second code generator configured to increase or decrease a value of second impedance calibration signals in response to the output signal of the second comparator,

a second driver configured to have its internal resistance value calibrated in response to the impedance calibration signals, and

a third driver configured to distribute the external voltage at a distribution ratio of a calibrated internal resistance value of the third driver and the internal resistance value of the second driver and output a distributed voltage as the second conversion voltage in response to the second impedance calibration signals.

13. The impedance calibration circuit according to claim 12 , wherein the second driver is a NMOS driver.

14. The impedance calibration circuit according to claim 12 , wherein the third driver is a PMOS driver.