Methods of manufacturing semiconductor device

1. A method of manufacturing a semiconductor device, the method comprising:

forming first auxiliary patterns;

alternately forming first material layers and second material layers on sidewalls of the first auxiliary patterns so that a gap region between the first auxiliary patterns adjacent to each other is filled;

removing the second material layers; and

forming charge storage layers in a nanowire form by filling the regions from which the second material layers have been removed with respective metal layers.

2. The method of claim 1 , wherein removing the second material layers is performed by a wet etch process.

3. The method of claim 1 , wherein alternately forming the first material layers and the second material layers comprises alternately growing the first material layers and the second material layers having a high etch selectivity to the first material layers by a selective epitaxial growth (SEG) using the first auxiliary patterns as seeds.

4. The method of claim 1 , wherein alternately forming the first material layers and the second material layers comprises:

forming seed layers on sidewalls of the first auxiliary patterns; and

alternately growing the first material layers and the second material layers, having a high etch selectivity to the first material layers, by an SEG process using the seed layers.

5. The method of claim 1 , wherein alternately forming the first material layers and the second material layers comprises alternately forming the first material layers and the second material layers, having a high etch selectivity to the first material layers, on sidewalls of the first auxiliary patterns by an atomic layer deposition (ALD) process.

6. The method of claim 5 , wherein alternately forming the first material layers and the second material layers comprises:

depositing the first material layer or the second material layer on sidewalls of the first auxiliary patterns and at a bottom of the gap region between the first auxiliary patterns, and

removing the first material layer or the second material layer formed at the bottom of the gap region in a purge process.

7. The method of claim 1 , further comprising:

removing the first auxiliary patterns after forming the charge storage layers;

forming a charge blocking layer on results from which the first auxiliary patterns have been removed;

forming a conductive layer for gate lines on the charge blocking layer; and

forming the gate lines by etching the conductive layer for the gate lines, the charge blocking layer, the charge storage layers, and the first material layers.

8. The method of claim 1 , further comprising:

forming a charge blocking layer on the formed charge storage layers;

forming a conductive layer for gate lines on the charge blocking layer; and

forming the gate lines by etching the conductive layer for the gate lines, the charge blocking layer, the first auxiliary patterns, the charge storage layers, and the first material layers.

9. A method of manufacturing a semiconductor device, the method comprising:

forming first auxiliary patterns;

alternately forming first material layers and second material layers on sidewalls of the first auxiliary patterns so that a gap region between the first auxiliary patterns adjacent to each other is filled;

removing the second material layers; and

forming charge storage layers in a dot form including nanodots by filling the regions from which the second material layers have been removed with the nanodots.

10. The method of claim 9 , wherein removing the second material layers comprises selectively removing part of each of the second material layers so that the second material layers remain in a dot form.

11. The method of claim 10 , wherein selectively removing the second material layers comprises:

forming an interlayer insulating layer on the first material layers and the second material layers which have been alternately formed;

forming second auxiliary patterns, disposed to cross the first auxiliary patterns, on the interlayer insulating layer;

alternately forming third material layers and fourth material layers on sidewalls of the second auxiliary patterns so that a gap region between the second auxiliary patterns adjacent to each other is filled;

removing the fourth material layers between the adjacent second auxiliary patterns;

etching the interlayer insulating layer exposed by removing the fourth material layers; and

etching the second material layers between the adjacent first auxiliary patterns exposed by etching the interlayer insulating layer.

12. The method of claim 11 , further comprising removing the second auxiliary patterns, the third material layers that remain between the second auxiliary patterns and the interlayer insulating layer, before forming the charge storage layers.

13. A method of manufacturing a semiconductor device, the method comprising:

forming first auxiliary patterns;

alternately forming first material layers and second material layers on sidewalls of the first auxiliary patterns so that a gap region between the first auxiliary patterns adjacent to each other is filled;

forming an interlayer insulating layer on the first material layers and the second material layers which have been alternately formed;

forming second auxiliary patterns, disposed to cross the first auxiliary patterns, on the interlayer insulating layer;

alternately forming third material layers and fourth material layers on sidewalls of the second auxiliary patterns so that a gap region between the second auxiliary patterns adjacent to each other is filled;

removing the fourth material layers between the adjacent second auxiliary patterns;

etching the interlayer insulating layer exposed by removing the fourth material layers;

etching the second material layers exposed by etching the interlayer insulating layer; and

forming charge storage layers in respective regions from which the second material layers have been etched.

14. The method of claim 13 , further comprising:

removing the second auxiliary patterns, the third material layers that remain between the second auxiliary patterns and the interlayer insulating layer, before forming the charge storage layers;

removing the first auxiliary patterns after forming the charge storage layers;

forming a charge blocking layer on results from which the first auxiliary patterns have been removed;

forming a conductive layer for gate lines on the charge blocking layer; and

forming the gate lines by etching the conductive layer for the gate lines, the charge blocking layer, and the first material layers.

15. The method of claim 13 , further comprising:

removing the second auxiliary patterns, the third material layers that remain between the second auxiliary patterns and the interlayer insulating layer, before forming the charge storage layers;

forming a charge blocking layer on the formed charge storage layers;

forming a conductive layer for gate lines on the charge blocking layer; and

forming the gate lines by etching the conductive layer for the gate lines, the charge blocking layer, the first auxiliary patterns, and the first material layers.