Receiver circuit
View Patent ↗A receiver circuit includes a buffering unit configured to buffer an input signal and generate a buffering signal; a variation detection unit configured to generate a control signal according to a level of a reference voltage; a driving unit configured to drive the buffering signal and generate an output signal; and a compensation unit configured to control a slew rate of the output signal in response to the control signal.
1. A receiver circuit comprising:
a buffering unit configured to buffer an input signal and generate a buffering signal;
a variation detection unit configured to generate a control signal according to a level of a reference voltage;
a driving unit configured to drive the buffering signal and generate an output signal; and
a compensation unit configured to control a slew rate of the output signal in response to the control signal,
wherein the buffering unit compares a level of the input signal and the level of the reference voltage, and determines a voltage level of the buffering signal.
2. The receiver circuit according to claim 1 , wherein the compensation unit determines an amount of current which flows from the driving unit to a ground terminal, in response to the control signal.
3. The receiver circuit according to claim 2 , wherein the driving unit comprises:
a first transistor having a gate which is inputted with the buffering signal and a source to which the external voltage is applied; and
a second transistor having a gate which is inputted with the buffering signal, a drain to which a drain of the first transistor is connected, and a source to which the compensation unit is connected,
wherein the output signal is outputted from a node to which the drains of the first transistor and the second transistor are connected.
4. The receiver circuit according to claim 3 , wherein the compensation unit comprises:
a third transistor having a gate which is inputted with the control signal, a drain to which the source of the second transistor is connected, and a source to which the ground terminal is connected.
5. The receiver circuit according to claim 1 , wherein the variation detection unit comprises:
a modeling buffering section configured to buffer the reference voltage and generate a detection signal;
a voltage dividing section configured to divide an external voltage and output a divided voltage; and
a comparing section configured to compare a voltage level of the detection signal and a level of the divided voltage and generate the control signal.
6. The receiver circuit according to claim 5 , wherein the modeling buffering section is configured in a similar way as the buffering unit.
7. The receiver circuit according to claim 5 , wherein the modeling buffering section generates the detection signal in correspondence to a level difference between the reference voltage and a ground voltage.
8. The receiver circuit according to claim 6 , wherein the modeling buffering section comprises:
a fourth transistor having a source to which the external voltage is applied;
a fifth transistor having a gate and drain to which the gate of the fourth transistor is connected, and a source to which the external voltage is applied;
a sixth transistor having a gate which is applied with the reference voltage and a drain to which the drain of the fourth transistor is connected;
a seventh transistor having a gate to which the ground voltage is applied and a drain to which the drain of the fifth transistor is connected; and
an eighth transistor having a gate to which an enable signal is inputted, a drain to which a node connected with the sources of the sixth and seventh transistors is connected, and a source to which the ground voltage is applied,
wherein the detection signal is outputted from a note to which the drains of the fourth and sixth transistors are connected.
9. The receiver circuit according to claim 6 , wherein the modeling buffering section comprises:
a fourth transistor having a source to which the external voltage is applied;
a fifth transistor having a gate and drain to which the gate of the fourth transistor is connected, and a source to which the external voltage is applied;
a sixth transistor having a gate which is applied with the reference voltage and a drain to which the drain of the fourth transistor is connected;
a seventh transistor having a gate to which the ground voltage is applied and a drain to which the drain of the fifth transistor is connected; and
an eighth transistor having a gate to which an the control signal is inputted, a drain to which a node connected with the sources of the sixth and seventh transistors is connected, and a source to which the ground voltage is applied,
wherein the detection signal is outputted from a note to which the drains of the fourth and sixth transistors are connected.
10. A receiver circuit comprising:
a buffering unit configured to buffer an input signal of a CML (current mode logic) level and generate a buffering signal;
a driving unit configured to drive the buffering signal and generate an output signal of a CMOS (complementary metal-oxide semiconductor) level; and
a variation compensation block having a modeling buffering section which is configured in a similar way as the buffering unit, and configured to increase or decrease a slew rate of the output signal in response to an output of the modeling buffering section,
wherein the buffering unit generates the buffering signal by comparing a level of a reference voltage and a voltage level of the input signal.
11. The receiver circuit according to claim 10 , wherein the variation compensation block comprises:
a variation detection unit configured to compare a level of the output of the modeling buffering section and a level of an external voltage, and generate a control signal; and
a compensation unit configured to increase or decrease an amount of current which flows from the driving unit to a ground terminal, in response to the control signal.
12. The receiver circuit according to claim 11 , wherein the variation detection unit comprises:
the modeling buffering section configured to compare the level of the reference voltage and a level of a ground voltage, and generate a detection signal;
a voltage dividing section configured to voltage-divide the external voltage and generate a divided voltage; and
a comparing section configured to compare a voltage level of the detection signal and the level of the external voltage, and generate the control signal.
13. The receiver circuit according to claim 10 , wherein the driving unit comprises:
a first transistor having a gate which is inputted with the buffering signal and a source to which the external voltage is applied; and
a second transistor having a gate which is inputted with the buffering signal, a drain to which a drain of the first transistor is connected, and a source to which the compensation unit is connected,
wherein the output signal is outputted from a node to which the drains of the first transistor and the second transistor are connected.
14. The receiver circuit according to claim 13 , wherein the compensation unit comprises:
a third transistor having a gate which is inputted with the control signal, a drain to which the source of the second transistor is connected, and a source to which the ground terminal is connected.
15. A receiver circuit comprising:
a buffering unit configured to buffer an input signal and generate a buffering signal;
a driving unit configured to pull down an output node when a voltage level of the buffering signal is equal to or higher than a preset voltage level, and pull up the output node when the voltage level of the buffering signal is equal to or lower than the preset voltage level; and
a variation compensation block having a modeling buffering section which is configured in a similar way as the buffering unit, and configured to control a pull-down driving force of the output node in response to an output of the modeling buffering section,
wherein the buffering unit generates the buffering signal by comparing a level of a reference voltage and a voltage level of the input signal.
16. The receiver circuit according to claim 15 , wherein the driving unit comprises:
a pull-up section configured to pull up the output node in response to the voltage level of the buffering signal; and
a pull-down section configured to pull down the output node in response to the voltage level of the buffering signal.
17. The receiver circuit according to claim 16 , wherein the variation compensation block comprises:
a variation detection unit configured to generate a control signal in response to a voltage level difference between a reference voltage and a ground voltage; and
a compensation unit configured to control a pull-down driving force of the pull-down section in response to the control signal.
18. The receiver circuit according to claim 17 , wherein the compensation unit comprises:
a transistor configured to control an amount of current which flows from the pull-down section to a ground terminal, in response to the control signal,
wherein the transistor has a gate which is inputted with the control signal, a drain to which the pull-down section is connected, and a source to which the ground terminal is connected.