IP Library Granted Patent US 8,518,785
Granted Patent B2
US 8,518,785 · App. 13/603,577 · Granted Aug 27, 2013

Semiconductor device and method of manufacturing the same

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Quick Facts
Patent No.
US 8,518,785
App. No.
13/603,577
Granted
Aug 27, 2013
Kind
B2
Abstract

A first p-type SiGe mixed crystal layer is formed by an epitaxial growth method in a trench, and a second p-type SiGe mixed crystal layer is formed. On the second SiGe mixed crystal layer, a third p-type SiGe mixed crystal layer is formed. The height of an uppermost surface of the first SiGe mixed crystal layer from the bottom of the trench is lower than the depth of the trench with the surface of the silicon substrate being the standard. The height of an uppermost surface of the second SiGe mixed crystal layer from the bottom of the trench is higher than the depth of the trench with the surface of the silicon substrate being the standard. Ge concentrations in the first and third SiGe mixed crystal layers are lower than a Ge concentration in the second SiGe mixed crystal layer.

Claims (56)

1. A method of manufacturing a semiconductor device, comprising:

forming a gate insulating film on a silicon substrate;

forming a gate electrode on the gate insulating film;

performing ion-implantation into the silicon substrate using the gate electrode as a mask;

forming a side wall insulating film on sidewall of the gate electrode;

forming a trench in the silicon substrate using the gate electrode and the side wall insulating film as masks;

forming a first crystal layer in the trench;

forming a second crystal layer on the first crystal layer; and

forming a silicide layer on the second crystal layer,

wherein

a top surface of the first crystal layer is located at the same height or higher than an interface between the silicon substrate and the gate insulating film, and

the second crystal layer has a lattice constant closer to a lattice constant of silicon than a lattice constant of the first crystal layer.

2. A method of manufacturing a semiconductor device, comprising:

forming a gate insulating film on a silicon substrate;

forming a gate electrode on the gate insulating film;

performing ion-implantation into the silicon substrate using the gate electrode as a mask;

forming a side wall insulating film on sidewall of the gate electrode;

forming a trench in the silicon substrate using the gate electrode and the side wall insulating film as masks; forming a first crystal layer in the trench;

forming a second crystal layer on the first crystal layer; and

forming a silicide layer on the second crystal layer,

wherein

a top surface of the first crystal layer is located at the same height or higher than an interface between the silicon substrate and the gate insulating film,

the first crystal layer is constituted of silicon germanium having a first germanium concentration, and

the second crystal layer is constituted of silicon germanium having a second germanium concentration which is lower than the first germanium concentration.

3. The method of manufacturing a semiconductor device according to claim 2 , wherein

the first germanium concentration is 20 atom % or higher, and the second germanium concentration is lower than 20 atom %.

4. The method of manufacturing a semiconductor device according to claim 2 , wherein

the first crystal layer is formed at a first growing temperature, and

the second crystal layer is formed at a second growing temperature which is higher than the first growing temperature.

5. A method of manufacturing a semiconductor device, comprising:

forming a gate insulating film on a silicon substrate;

forming a gate electrode on the gate insulating film;

performing ion-implantation into the silicon substrate using the gate electrode as a mask;

forming a side wall insulating film on sidewall of the gate electrode;

forming a trench in the silicon substrate using the gate electrode and the side wall insulating film as masks;

forming a first crystal layer in the trench;

forming a second crystal layer on the first crystal layer; and

forming a silicide layer on the second crystal layer,

wherein

a top surface of the first crystal layer is located at the same height or lower than an interface between the silicon substrate and the gate insulating film, and

the first crystal layer has a lattice constant closer to a lattice constant of silicon than a lattice constant of the second crystal layer.

6. A method of manufacturing a semiconductor device, comprising:

forming a gate insulating film on a silicon substrate;

forming a gate electrode on the gate insulating film; performing ion-implantation into the silicon substrate using the gate electrode as a mask;

forming a trench in the silicon substrate;

forming a first crystal layer in the trench;

forming a second crystal layer on the first crystal layer; and

forming a silicide layer on the second crystal layer,

wherein

a top surface of the first crystal layer is located at the same height or lower than an interface between the silicon substrate and the gate insulating film,

the first crystal layer is constituted of silicon germanium having a first germanium concentration, and

the second crystal layer is constituted of silicon germanium having a second germanium concentration which is higher than the first germanium concentration.

7. The method of manufacturing a semiconductor device according to claim 6 , wherein

the first germanium concentration is lower than 20 atom %, and the second germanium concentration is 20 atom % or higher.

8. The method of manufacturing a semiconductor device according to claim 6 , wherein

the first crystal layer is formed at a first growing temperature, and the second crystal layer is formed at a second growing temperature which is lower than the first growing temperature.

Assignments (10)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2025
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 073964/0516 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 27, 2024
From: FUJITSU LIMITED
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 069454/0333 →
MERGER Recorded May 24, 2023
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU LIMITED
Reel/Frame 064221/0545 →
CHANGE OF NAME AND CHANGE OF ADDRESS Recorded Jul 16, 2020
From: AIZU FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053481/0962 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2020
From: FUJITSU SEMICONDUCTOR LIMITED
To: AIZU FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 053209/0468 →
CHANGE OF ADDRESS Recorded Dec 23, 2016
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 041188/0401 →
CHANGE OF NAME Recorded Oct 17, 2012
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 029143/0050 →
CORRECTIVE ASSIGNMENT TO CORRECT THE CONVEYANCE TYPE PREVIOUSLY RECORDED ON REEL 028973 FRAME 0410. ASSIGNOR(S) HEREBY CONFIRMS THE CORRECT CONVEYANCE TYPE IS ASSIGNMENT, NOT CHANGE OF NAME. Recorded Oct 11, 2012
From: FUJITSU LIMITED
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 029112/0168 →
CHANGE OF NAME Recorded Sep 14, 2012
From: FUJITSU LIMITED
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 028973/0410 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 5, 2012
From: SHIMAMUNE, YOSUKE; FUKUDA, MASAHIRO; KIM, YOUNG SUK; KATAKAMI, AKIRA; HATADA, AKIYOSHI; TAMURA, NAOYOSHI; OHTA, HIROYUKI
To: FUJITSU LIMITED
Reel/Frame 028900/0268 →