Exclusive OR circuit
View Patent ↗An exclusive OR circuit includes, inter alia: a low pass unit configured to apply a second data to an output node when a first data is at a low level and to apply the first data to the output node when the second data is at a low level, and a discharge unit configured to discharge a voltage level of the output node when the first and second data are at a high level.
1. An exclusive OR circuit comprising:
a low pass unit configured to apply a second data to an output node when a first data is at a low level, and to apply the first data to the output node when the second data is at a low level;
a high pass unit configured to output the second data as a discharge signal when the first data is at a high level, and to output the first data as the discharge signal when the second data is at a high level; and
a discharge unit configured to discharge a voltage level of the output node in response to the discharge signal.
2. The exclusive OR circuit according to claim 1 , wherein the discharge unit discharges the voltage level of the output node when the discharge signal is at a high level.
3. An exclusive OR circuit comprising:
a first transistor forming a source-drain path between a first input terminal and an output node and having a gate connected to a second input terminal;
a second transistor forming a source-drain path between the second input terminal and the output node and having a gate connected to the first input terminal;
a third transistor forming a source-drain path between the first ut terminal and a control node and having a gate connected to the second input terminal;
a fourth transistor forming a source-drain path between the second input terminal and the control node and having a gate connected to the first input terminal; and
a fifth transistor forming a source-drain path between the output node and a ground, and having a gate connected to the control node.
4. The exclusive OR circuit according to claim 3 , wherein the first and second transistors are PMOS transistors, and the third to fifth transistors are NMOS transistors.
5. A circuit capable of performing a logic operation comprising:
a low pass unit configured to apply a second data to an output node when a first data is at a low level, and to apply the first data to the output node when the second data is at a low level;
a high pass unit configured to output the second data as a discharge signal when the first data is at a high level, and to output the first data as the discharge signal when the second data is at a high level; and
a discharge unit configured to discharge a voltage level of the output node in response to the discharge signal.
6. The circuit according to claim 5 , wherein the discharge unit outputs the voltage level of the output node when the discharge signal is at a high level.