IP Library Granted Patent US 8,716,119
Granted Patent B2
US 8,716,119 · App. 13/605,848 · Granted May 6, 2014

Methods of forming transistor gates

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Quick Facts
Patent No.
US 8,716,119
App. No.
13/605,848
Granted
May 6, 2014
Kind
B2
Abstract

Some embodiments include methods of forming charge storage transistor gates and standard FET gates in which common processing is utilized for fabrication of at least some portions of the different types of gates. FET and charge storage transistor gate stacks may be formed. The gate stacks may each include a gate material, an insulative material, and a sacrificial material. The sacrificial material is removed from the FET and charge storage transistor gate stacks. The insulative material of the FET gate stacks is etched through. A conductive material is formed over the FET gate stacks and over the charge storage transistor gate stacks. The conductive material physically contacts the gate material of the FET gate stacks, and is separated from the gate material of the charge storage transistor gate stacks by the insulative material remaining in the charge storage transistor gate stacks. Some embodiments include gate structures.

Claims (16)

1. A method of forming a plurality of charge storage transistor gates and field effect transistor (FET) gates, comprising:

forming a stack over a semiconductor substrate; the stack comprising a gate dielectric material, a gate material over the gate dielectric material, an electrically insulative material over the gate material, a sacrificial material over the electrically insulative material, and a protective material over the sacrificial material;

patterning the stack into a plurality of pillars; some of the pillars being at charge storage transistor gate locations, and some of the pillars being at FET gate locations;

forming electrically insulative spacers along sidewalls of the pillars;

after forming the electrically insulative spacers, removing the protective material from over the sacrificial material;

removing the sacrificial material from all of the pillars to form cavities at the tops of all of the pillars; individual cavities being bounded by the electrically insulative material along the bottom, and by the spacers along the sides;

after removing the sacrificial material, removing at least some of the electrically insulative material of the pillars at the FET locations to extend the cavities through the electrically insulative material and expose the gate material, while not etching through the electrically insulative material of the pillars at the charge storage transistor locations;

forming a first electrically conductive material conformally within all of the cavities to partially fill the cavities and thereby narrow the cavities, the first electrically conductive material physically contacting the gate material within the extended cavities of the pillars at the FET gate locations, and being separated from the gate material of the pillars at the charge storage transistor gate locations by the electrically insulative material; and

forming second electrically conductive material within the narrowed cavities to entirely fill the cavities.

2. The method of claim 1 wherein the pillars and the spacers along the pillar sidewalls together form a plurality of spaced apart gate constructions, and further comprising, prior to the removal of the protective material, forming an electrically insulative material within spaces between the spaced apart gate constructions.

3. The method of claim 2 wherein the removing the protective material comprises planarization across the electrically insulative material and pillars; and wherein the planarization removes upper regions of the spacers during the removal of the protective material.

4. The method of claim 1 wherein the first electrically conductive material comprises a metal-containing composition.

5. The method of claim 1 wherein the first electrically conductive material comprises a metal nitride.

6. The method of claim 1 wherein the first electrically conductive material comprises one or both of tungsten nitride and tantalum nitride.

7. The method of claim 6 wherein the second electrically conductive material consists of one or more metals.

8. The method of claim 6 wherein the second electrically conductive material consists of tungsten.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 14, 2024
From: MICRON TECHNOLOGY, INC.
To: LODESTAR LICENSING GROUP LLC
Reel/Frame 068884/0654 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →